公开(公告)号：US20250007145A1

公开(公告)日：2025-01-02

申请号：US18216315

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Peter BAUMGARTNER ,  Richard GEIGER ,  Georgios C. DOGIAMIS ,  Steven CALLENDER ,  Telesphor KAMGAING ,  Jonathan C. JENSEN ,  Harald GOSSNER

IPC: H01Q1/22 ,  H01L25/10 ,  H01Q21/24

Abstract: Embodiments disclosed herein include communication dies for mm-wave and/or sub-terahertz wavelength communications. In an embodiment, a communications die comprises a substrate with a first face and a second face. In an embodiment, edge surfaces connect the first face to the second face. In an embodiment, a circuitry element is on the first face, and an antenna on at least one of the edge surfaces.

公开(公告)号：US20230101378A1

公开(公告)日：2023-03-30

申请号：US17448738

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Peter BAUMGARTNER ,  Joachim ASSENMACHER ,  Walther LUTZ ,  Martin OSTERMAYR ,  Georg SEIDEMANN

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/532 ,  H01L49/02

Abstract: A semiconductor die is disclosed, including a plurality of transistors at a frontside of a semiconductor substrate, a backside inductor at a backside of the semiconductor substrate; and a frontside inductor at the frontside of the semiconductor substrate. The frontside inductor and the backside inductor are inductively coupled.

公开(公告)号：US20240429155A1

公开(公告)日：2024-12-26

申请号：US18214252

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Mamatha YAKKEGONDI VIRUPAKSHAPPA ,  Peter BAUMGARTNER ,  Carla MORAN GUIZAN ,  Philipp RIESS ,  Michael LANGENBUCH ,  Roshini SACHITHANANDAN ,  Jonathan C. JENSEN

IPC: H01L23/522 ,  G06F30/367

Abstract: Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. The metal plate is coupled to the first metal lines or the second metal lines by vias.

公开(公告)号：US20240429269A1

公开(公告)日：2024-12-26

申请号：US18214244

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Peter BAUMGARTNER ,  Mamatha YAKKEGONDI VIRUPAKSHAPPA ,  Carla MORAN GUIZAN ,  Roshini SACHITHANANDAN ,  Philipp RIESS ,  Michael LANGENBUCH ,  Jonathan C. JENSEN

IPC: H01G4/30

Abstract: Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. A dielectric liner layer is between the alternating first metal lines and second metal lines and the metal plate.

公开(公告)号：US20210305245A1

公开(公告)日：2021-09-30

申请号：US16833094

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Richard HUDECZEK ,  Philipp RIESS ,  Richard GEIGER ,  Peter BAUMGARTNER

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

Abstract: Embodiments disclosed herein include resonators, such as resonant fin transistors (RFTs). In an embodiment a resonator comprises a substrate, a set of contact fins over the substrate, a first contact proximate to a first end of the set of contact fins, and a second contact proximate to a second end of the set of contact fins. In an embodiment, the resonator further comprises a set of skip fins over the substrate and adjacent to the set of contact fins. In an embodiment, the resonator further comprises a gate electrode over the set of contact fins and the set of skip fins, wherein the gate electrode is between the first contact and the second contact.

公开(公告)号：US20250006837A1

公开(公告)日：2025-01-02

申请号：US18214904

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Richard GEIGER ,  Peter BAUMGARTNER

IPC: H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/423

Abstract: Structures having vertical-transport field effect transistors (FETs) with bottom source connection are described. In an example, an integrated circuit structure includes a channel structure above a substrate. A gate structure is laterally surrounding the channel structure. A drain structure is above the gate structure and on the channel structure. A metal source structure is below the substrate and vertically beneath the channel structure. A conductive via is through the substrate, the conductive via coupling the metal source structure to the channel structure.

公开(公告)号：US20240385307A1

公开(公告)日：2024-11-21

申请号：US18318754

申请日：2023-05-17

Applicant: Intel Corporation

Inventor： Lukas SCHRAMM ,  Peter BAUMGARTNER

IPC: G01S13/34 ,  G01S7/35

Abstract: A non-transitory computer readable medium having instructions stored therein that when executed by a processor cause the processor to: determine a time difference between a first reference point of a first signal and a second reference point of a second signal, the first signal modulated with a first frequency, and the second signal modulated with a second frequency different from the first frequency; to determine a phase noise based on the determined time difference; and to use the determined phase noise for processing a signal associated with the first signal.

公开(公告)号：US20230197566A1

公开(公告)日：2023-06-22

申请号：US17644802

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Wolfgang MOLZER ,  Peter BAUMGARTNER ,  Thomas WAGNER ,  Joachim SINGER ,  Klaus HEROLD ,  Michael LANGENBUCH

IPC: H01L23/433 ,  H01L23/473 ,  H01L23/40 ,  H01L21/48

CPC classification number: H01L23/433 ,  H01L21/4871 ,  H01L23/473 ,  H01L23/4012 ,  H01L2023/4068

Abstract: A semiconductor die is provided. The semiconductor die includes a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure and a trench extending from a backside of the semiconductor substrate into the semiconductor substrate. A length of the trench is equal or larger than a lateral dimension of the semiconductor substrate.

公开(公告)号：US20230094594A1

公开(公告)日：2023-03-30

申请号：US17448732

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Wolfgang MOLZER ,  Klaus HEROLD ,  Joachim SINGER ,  Peter BAUMGARTNER ,  Michael LANGENBUCH ,  Thomas WAGNER ,  Bernd WAIDHAS

IPC: H01L25/065 ,  H01L27/088 ,  H01L23/498 ,  H01L23/367

Abstract: A semiconductor device is disclosed, comprising a first semiconductor die comprising a plurality of transistors; a second semiconductor die comprising power supply circuitry configured to generate a supply voltage for the plurality of transistors of the first semiconductor die; and a heat spreader structure. A power supply routing for a reference voltage or a power supply voltage which extends from the heat spreader structure through the second semiconductor die to the first semiconductor die.