公开(公告)号：US20220107808A1

公开(公告)日：2022-04-07

申请号：US17552843

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Anand K. ENAMANDRAM ,  Eswaramoorthi NALLUSAMY ,  Ramamurthy KRITHIVAS ,  Cheng-Wein LIN ,  Irene JOHANSEN

IPC: G06F9/30 ,  G06F9/38

Abstract: Methods and apparatus to reduce register access latency in split-die SoC designs. The method is implemented on a platform including a legacy socket and one or more non-legacy (NL) sockets comprising split-die System-on-Chips (SoC)s including multiple dielets interconnected with a plurality of Embedded Multi-Die Interconnect Bridges (EMIBs). The dielets include core dielets having cores, cache controllers and memory controllers. The method provides an affinity between a control and status registers (CSRs) memory range for the NL sockets such that CSRs in the memory controllers for multiple core dielets are programmed using transactions forwarded along core-to-cache controller datapaths that avoid crossing EMIBs. In one aspect, a transient map of address ranges is created that includes a respective Sub-NUMA Cluster (SNC) range allocated for the NL sockets, with a range of CSR addresses for accessing CSRs in the memory controllers for the NL sockets being stored in the respective SNC ranges.