公开(公告)号：US20190042514A1

公开(公告)日：2019-02-07

申请号：US16049607

申请日：2018-07-30

Applicant: Intel Corporation

Inventor： Anand K. ENAMANDRAM ,  Sivakumar RADHAKRISHNAN ,  Jayasekhar THOLIYIL ,  Tina C. ZHONG ,  Malay TRIVEDI

IPC: G06F13/40 ,  G06F9/4401 ,  G06F9/445 ,  G06F13/16 ,  G06F13/42

Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.

公开(公告)号：US20240272911A1

公开(公告)日：2024-08-15

申请号：US18645295

申请日：2024-04-24

Applicant: Intel Corporation

Inventor： Ramamurthy KRITHIVAS ,  Eswaramoorthi NALLUSAMY ,  Anand K. ENAMANDRAM ,  Mahesh S. NATU ,  Eric J. DEHAEMER ,  Filip SCHMOLE ,  Bharat S. PILLILLI

IPC: G06F9/4401

CPC classification number: G06F9/4403

Abstract: Examples described herein relate to an apparatus that includes an interface and circuitry to: prior to boot of a processor, configure a memory address decoder to increase a memory region size associated with firmware access from a first size to a second size, wherein the second size is larger than the first size. In some examples, the memory address decoder is to decode an address space in a Serial Peripheral Interface (SPI) flash device to determine a location of a Firmware Interface Table (FIT) in the second size of the memory region and the second circuitry is to access an entry in the FIT to determine a location of a boot firmware.

公开(公告)号：US20240264759A1

公开(公告)日：2024-08-08

申请号：US18622005

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Anand K. ENAMANDRAM ,  Kerry VANDER KAMP ,  Mahesh S. NATU ,  Robert A. BRANCH

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0683

Abstract: A Cloud Service Provider reconfigures a memory subsystem during routine operation, while minimizing the amount of time a server is not online. Server downtime is reduced by offloading reconfiguration of system memory to the operating system with platform assistance. The operating system enumerates potential memory configurations of the memory subsystem with associated performance characteristics in an abstracted manner and performs reconfiguration of the memory subsystem without a cold reset. When reconfiguration of the memory subsystem is deemed necessary by the operating system, the operating system examines the enumerated memory subsystem configurations provided by system firmware. After selecting the memory subsystem configuration, the operating system initiates a reconfiguration process. The reconfiguration process saves any existing memory context to an auxiliary device, requests system firmware to perform the memory subsystem reconfiguration, and restores the existing memory context from the auxiliary device after the memory subsystem reconfiguration has been completed.

公开(公告)号：US20220107808A1

公开(公告)日：2022-04-07

申请号：US17552843

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Anand K. ENAMANDRAM ,  Eswaramoorthi NALLUSAMY ,  Ramamurthy KRITHIVAS ,  Cheng-Wein LIN ,  Irene JOHANSEN

IPC: G06F9/30 ,  G06F9/38

Abstract: Methods and apparatus to reduce register access latency in split-die SoC designs. The method is implemented on a platform including a legacy socket and one or more non-legacy (NL) sockets comprising split-die System-on-Chips (SoC)s including multiple dielets interconnected with a plurality of Embedded Multi-Die Interconnect Bridges (EMIBs). The dielets include core dielets having cores, cache controllers and memory controllers. The method provides an affinity between a control and status registers (CSRs) memory range for the NL sockets such that CSRs in the memory controllers for multiple core dielets are programmed using transactions forwarded along core-to-cache controller datapaths that avoid crossing EMIBs. In one aspect, a transient map of address ranges is created that includes a respective Sub-NUMA Cluster (SNC) range allocated for the NL sockets, with a range of CSR addresses for accessing CSRs in the memory controllers for the NL sockets being stored in the respective SNC ranges.

公开(公告)号：US20190042348A1

公开(公告)日：2019-02-07

申请号：US15859474

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Ramamurthy KRITHIVAS ,  Anand K. ENAMANDRAM ,  Eswaramoorthi NALLUSAMY ,  Russell J. WUNDERLICH ,  Krishnakanth V. SISTLA

IPC: G06F11/07

Abstract: Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.