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    DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES
    1.
    发明申请
    DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES 有权

    公开(公告)号：US20210326285A1

    公开(公告)日：2021-10-21

    申请号：US17207135

    申请日：2021-03-19

    申请人： Intel Corporation

    发明人： Balaji PARTHASARATHY ,  Ramamurthy KRITHIVAS ,  Bradley A. BURRES ,  Pawel SZYMANSKI ,  Yi-Feng LIU

    IPC分类号： G06F13/40 ,  G06F9/4401 ,  G06F9/445

    摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

    TECHNOLOGIES TO EXPAND PIN COUNT
    3.
    发明公开
    TECHNOLOGIES TO EXPAND PIN COUNT 审中-公开

    公开(公告)号：US20240281375A1

    公开(公告)日：2024-08-22

    申请号：US18651039

    申请日：2024-04-30

    申请人： Intel Corporation

    发明人： Ramamurthy KRITHIVAS ,  Yi ZENG ,  Rahul SHAH ,  Krzysztof WOJCIK

    IPC分类号： G06F12/08

    CPC分类号： G06F12/08 ,  G06F2212/16

    摘要： Examples described herein relate to communications with a bootable processor. Some examples include allocating memory address space to provide access to communications over general purpose input output (GPIO)-consistent pins, wherein the GPIO-consistent pins comprise pins coupled to the bootable processor and a pin of the pins coupled to the bootable processor receives or transmits communication for multiple platform GPIO pins.

    DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES
    4.
    发明公开
    DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES 审中-公开

    公开(公告)号：US20230367729A1

    公开(公告)日：2023-11-16

    申请号：US18199042

    申请日：2023-05-18

    申请人： Intel Corporation

    发明人： Balaji PARTHASARATHY ,  Ramamurthy KRITHIVAS ,  Bradley BURRES ,  Pawel SZYMANSKI ,  Yi-Feng LIU

    IPC分类号： G06F13/40 ,  G06F9/4401 ,  G06F9/445

    CPC分类号： G06F13/4027 ,  G06F9/4403 ,  G06F9/4418 ,  G06F9/44505 ,  G06F13/4022

    摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

    DEVICE CAPABILITY ADDRESSABLE NETWORK
    5.
    发明申请
    DEVICE CAPABILITY ADDRESSABLE NETWORK 审中-公开
    设备能力可寻址网络

    公开(公告)号：US20160248674A1

    公开(公告)日：2016-08-25

    申请号：US14129661

    申请日：2013-09-27

    申请人： INTEL CORPORATION

    发明人： Mrittika Mrittika GANGULI ,  Deepak S ,  Mohan J. KUMAR ,  Ramamurthy KRITHIVAS

    IPC分类号： H04L12/743 ,  H04L12/715 ,  H04L12/725 ,  H04L12/721

    CPC分类号： H04L45/7453 ,  H04L45/302 ,  H04L45/44 ,  H04L45/64 ,  H04L67/10 ,  H04L67/303

    摘要： Technologies for using a hash key for communicating via an overlay network include a computing device for receiving a hash key that includes a hash indicative of a requested characteristic of a target computing device and another hash indicative of another requested characteristic of the target computing device. Such technologies may also include parsing the hash key to obtain the hash and the another hash; sending a message that includes the hash to a group of other computing devices; receiving a response message from a computing device of the group indicating that the computing device of the group includes a characteristic matching the requested characteristic; and sending another message that includes the second hash to the computing device of the group in response to receipt of the response message from the computing device of the group.

    摘要翻译： 使用用于通过覆盖网络进行通信的散列密钥的技术包括用于接收散列密钥的计算设备，所述散列密钥包括指示目标计算设备的请求特性的哈希，以及指示所述目标计算设备的另一请求特性的另一散列。 这样的技术还可以包括解析散列密钥以获得散列和另一散列; 将包括所述散列的消息发送到一组其他计算设备; 从所述组的计算设备接收指示所述组的计算设备包括与所请求的特性匹配的特性的响应消息; 以及响应于从所述组的所述计算设备接收到所述响应消息，向所述组的所述计算设备发送包括所述第二散列的另一个消息。

    METHOD TO REDUCE REGISTER ACCESS LATENCY IN SPLIT-DIE SOC DESIGNS
    6.
    发明申请
    METHOD TO REDUCE REGISTER ACCESS LATENCY IN SPLIT-DIE SOC DESIGNS 有权

    公开(公告)号：US20220107808A1

    公开(公告)日：2022-04-07

    申请号：US17552843

    申请日：2021-12-16

    申请人： Intel Corporation

    发明人： Anand K. ENAMANDRAM ,  Eswaramoorthi NALLUSAMY ,  Ramamurthy KRITHIVAS ,  Cheng-Wein LIN ,  Irene JOHANSEN

    IPC分类号： G06F9/30 ,  G06F9/38

    摘要： Methods and apparatus to reduce register access latency in split-die SoC designs. The method is implemented on a platform including a legacy socket and one or more non-legacy (NL) sockets comprising split-die System-on-Chips (SoC)s including multiple dielets interconnected with a plurality of Embedded Multi-Die Interconnect Bridges (EMIBs). The dielets include core dielets having cores, cache controllers and memory controllers. The method provides an affinity between a control and status registers (CSRs) memory range for the NL sockets such that CSRs in the memory controllers for multiple core dielets are programmed using transactions forwarded along core-to-cache controller datapaths that avoid crossing EMIBs. In one aspect, a transient map of address ranges is created that includes a respective Sub-NUMA Cluster (SNC) range allocated for the NL sockets, with a range of CSR addresses for accessing CSRs in the memory controllers for the NL sockets being stored in the respective SNC ranges.