公开(公告)号：US12100662B2

公开(公告)日：2024-09-24

申请号：US17127304

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

IPC: H01L23/538 ,  H01L21/50 ,  H01L23/50 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/50 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

公开(公告)号：US20220199537A1

公开(公告)日：2022-06-23

申请号：US17127304

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

IPC: H01L23/538 ,  H01L23/50 ,  H01L25/065 ,  H01L21/50

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.