公开(公告)号：US20240258296A1

公开(公告)日：2024-08-01

申请号：US18630302

申请日：2024-04-09

申请人： Intel Corporation

发明人： Adel A. Elsherbini ,  Georgios Dogiamis ,  Shawna M. Liff ,  Zhiguo Qian ,  Johanna M. Swan

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/532 ,  H01L23/538 ,  H01L23/66

CPC分类号： H01L25/18 ,  H01L23/5329 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/17 ,  H01L2223/6627 ,  H01L2224/0237

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a first die, having opposing first and second surfaces, in a first dielectric layer, wherein the first dielectric layer is between a second dielectric layer and the surface of the package substrate, and the first surface of the first die is coupled to the surface of the package substrate; a second die, having opposing first and second surfaces, in the second dielectric layer, and wherein the second dielectric layer is between the first dielectric layer and a third dielectric layer; a third die, having opposing first and second surfaces, in the third dielectric layer, wherein the first surface of the third die is coupled to the surface of the package substrate by a conductive pillar; and a conductive, radio frequency shield structure surrounding the conductive pillar.

公开(公告)号：US20230420358A1

公开(公告)日：2023-12-28

申请号：US17851957

申请日：2022-06-28

申请人： Intel Corporation

发明人： Cemil S. Geyik ,  Kristof Kuwawi Darmawikarta ,  Zhiguo Qian ,  Kemal Aygun ,  Jung Kyu Han ,  Srinivas V. Pietambaram ,  Rengarajan Shanmugam ,  Robert L. Sankman

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L21/48

CPC分类号： H01L23/49894 ,  H01L23/49822 ,  H01L23/5383 ,  H01L21/4857

摘要： Disclosed herein are silver-coated conductive structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a first material layer on a top surface and on side surfaces of the conductive line, the first material layer including silver, and a second material layer on the first material layer, the second material layer including silicon or aluminum, and one or more of nitrogen and oxygen.

公开(公告)号：US11450560B2

公开(公告)日：2022-09-20

申请号：US16140398

申请日：2018-09-24

申请人： Intel Corporation

发明人： Krishna Bharath ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Kaladhar Radhakrishnan ,  Zhiguo Qian ,  Johanna M. Swan

IPC分类号： H01L21/768

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

公开(公告)号：US11387188B2

公开(公告)日：2022-07-12

申请号：US17091657

申请日：2020-11-06

申请人： Intel Corporation

发明人： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/31

摘要： Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

公开(公告)号：US20220093725A1

公开(公告)日：2022-03-24

申请号：US17025209

申请日：2020-09-18

申请人： Intel Corporation

发明人： Adel A. Elsherbini ,  Mohammad Enamul Kabir ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Feras Eid

IPC分类号： H01L49/02 ,  H01L23/49 ,  H01L23/492

摘要： Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

公开(公告)号：US11276635B2

公开(公告)日：2022-03-15

申请号：US16636620

申请日：2017-09-29

申请人： Intel Corporation

发明人： Sujit Sharan ,  Kemal Aygun ,  Zhiguo Qian ,  Yidnekachew Mekonnen ,  Zhichao Zhang ,  Jianyong Xie

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/00

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US11244890B2

公开(公告)日：2022-02-08

申请号：US17074820

申请日：2020-10-20

申请人： Intel Corporation

发明人： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC分类号： H01L23/498 ,  H01L21/48

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US11222848B2

公开(公告)日：2022-01-11

申请号：US16634864

申请日：2017-09-28

申请人： Intel Corporation

发明人： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC分类号： H01L23/52 ,  H01L21/4763 ,  H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US11094633B2

公开(公告)日：2021-08-17

申请号：US16305758

申请日：2016-06-30

申请人： Intel Corporation

发明人： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim ,  Jackie C. Preciado

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

摘要： A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.

公开(公告)号：US11081434B2

公开(公告)日：2021-08-03

申请号：US16993112

申请日：2020-08-13

申请人： Intel Corporation

发明人： Zhiguo Qian ,  Kaladhar Radhakrishnan ,  Kemal Aygun

IPC分类号： H01L23/49 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/68

摘要： The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.