公开(公告)号：US11569198B2

公开(公告)日：2023-01-31

申请号：US16646974

申请日：2018-01-03

Applicant: Intel Corporation

Inventor： Edward Burton

IPC: H01L25/00 ,  H01L23/00

Abstract: Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

公开(公告)号：US20190245582A1

公开(公告)日：2019-08-08

申请号：US16383947

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Edward Burton

IPC: H04B3/32 ,  G06F15/173

CPC classification number: H04B3/32 ,  G06F15/173

Abstract: A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.

公开(公告)号：US20220199537A1

公开(公告)日：2022-06-23

申请号：US17127304

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

IPC: H01L23/538 ,  H01L23/50 ,  H01L25/065 ,  H01L21/50

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

公开(公告)号：US12164319B2

公开(公告)日：2024-12-10

申请号：US17128073

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Sathya Narasimman Tiagaraj ,  Gerald Pasdast ,  Edward Burton

IPC: G05F1/575 ,  G06F1/26

Abstract: A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.

公开(公告)号：US11043986B2

公开(公告)日：2021-06-22

申请号：US16383947

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Edward Burton

IPC: H04B3/32 ,  G06F15/173

Abstract: A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.

公开(公告)号：US12100662B2

公开(公告)日：2024-09-24

申请号：US17127304

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

IPC: H01L23/538 ,  H01L21/50 ,  H01L23/50 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/50 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

公开(公告)号：US11532984B2

公开(公告)日：2022-12-20

申请号：US16449129

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Edward Burton

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: Various embodiments provide a parallel arrangement of discontinuous conduction mode (DCM) voltage regulators to provide a regulated voltage to a load. The individual DCM voltage regulators may be triggered (e.g., switched to a charge state) when the regulated voltage falls below a lower threshold. Different DCM voltage regulators in the parallel arrangement may have different lower thresholds. In some embodiments, different DCM voltage regulators may include different inductance and/or transistor size (e.g., to tune the DCM voltage regulators to different current handling capabilities). Other embodiments may be described and claimed.

公开(公告)号：US12015009B2

公开(公告)日：2024-06-18

申请号：US18080610

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Edward Burton

IPC: H01L25/00 ,  H01L23/00

CPC classification number: H01L25/00 ,  H01L24/16 ,  H01L2224/16145

Abstract: Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

公开(公告)号：US20220197321A1

公开(公告)日：2022-06-23

申请号：US17128073

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Sathya Narasimman Tiagaraj ,  Gerald Pasdast ,  Edward Burton

IPC: G05F1/575 ,  G06F1/26

Abstract: A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.