公开(公告)号：US20190303743A1

公开(公告)日：2019-10-03

申请号：US16317497

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Swagath VENKATARAMANI ,  Dipankar DAS ,  Ashish RANJAN ,  Subarno BANERJEE ,  Sasikanth AVANCHA ,  Ashok JAGANNATHAN ,  Ajaya V. DURG ,  Dheemanth NAGARAJ ,  Bharat KAUL ,  Anand RAGHUNATHAN

IPC: G06N3/04 ,  G06N3/08

Abstract: Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.

公开(公告)号：US20240118892A1

公开(公告)日：2024-04-11

申请号：US18543357

申请日：2023-12-18

Applicant: Intel Corporation

Inventor： Swagath VENKATARAMANI ,  Dipankar DAS ,  Ashish RANJAN ,  Subarno BANERJEE ,  Sasikanth AVANCHA ,  Ashok JAGANNATHAN ,  Ajaya V. DURG ,  Dheemanth NAGARAJ ,  Bharat KAUL ,  Anand RAGHUNATHAN

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06N3/04 ,  G06N3/063 ,  G06N3/084

CPC classification number: G06F9/30145 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/52 ,  G06N3/04 ,  G06N3/063 ,  G06N3/084

Abstract: Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.