公开(公告)号：US09673966B2

公开(公告)日：2017-06-06

申请号：US14968616

申请日：2015-12-14

Applicant: Intel Corporation

Inventor： Dima Hammad ,  Vadim Levin ,  Amir Laufer ,  Ron Bar-Lev ,  Noam Familia ,  Itamar Levin

IPC: H04L7/00 ,  H04L1/00 ,  H03L7/08 ,  H03L7/093 ,  H03L7/107 ,  H04L1/20 ,  H04L1/24

CPC classification number: H04L7/0054 ,  H03L7/0807 ,  H03L7/093 ,  H03L7/1075 ,  H04L1/00 ,  H04L1/203 ,  H04L1/24 ,  H04L7/0016 ,  H04L7/0062 ,  H04L7/0079

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

公开(公告)号：US08989329B2

公开(公告)日：2015-03-24

申请号：US13836383

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Dima Hammad ,  Vadim Levin ,  Amir Laufer ,  Ron Bar-Lev ,  Noam Familia ,  Itamar Levin

IPC: H04L7/00

CPC classification number: H04L7/0054 ,  H03L7/0807 ,  H03L7/093 ,  H03L7/1075 ,  H04L1/00 ,  H04L1/203 ,  H04L1/24 ,  H04L7/0016 ,  H04L7/0062 ,  H04L7/0079

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

公开(公告)号：US09917685B2

公开(公告)日：2018-03-13

申请号：US15614470

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Dima Hammad ,  Vadim Levin ,  Amir Laufer ,  Ron Bar-Lev ,  Noam Familia ,  Itamar Levin

IPC: H04L7/00 ,  H04L1/00 ,  H03L7/107 ,  H03L7/093 ,  H03L7/08 ,  H04L1/20 ,  H04L1/24

CPC classification number: H04L7/0054 ,  H03L7/0807 ,  H03L7/093 ,  H03L7/1075 ,  H04L1/00 ,  H04L1/203 ,  H04L1/24 ,  H04L7/0016 ,  H04L7/0062 ,  H04L7/0079

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

公开(公告)号：US09215061B2

公开(公告)日：2015-12-15

申请号：US14667146

申请日：2015-03-24

Applicant: Intel Corporation

Inventor： Dima Hammad ,  Vadim Levin ,  Amir Laufer ,  Ron Bar-Lev ,  Noam Familia ,  Itamar Levin

IPC: H04L7/00 ,  H04L1/00 ,  H03L7/08 ,  H03L7/093 ,  H03L7/107

CPC classification number: H04L7/0054 ,  H03L7/0807 ,  H03L7/093 ,  H03L7/1075 ,  H04L1/00 ,  H04L1/203 ,  H04L1/24 ,  H04L7/0016 ,  H04L7/0062 ,  H04L7/0079

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract translation: 通常，本公开描述了通信系统中的眼宽测量和边缘化。 一种装置可以被配置为：响应于将边缘化时钟信号同步到接收机时钟信号，将相位检测器与被测接收机的CDR环路滤波器分离; 对环路滤波器施加裕度输入，边缘输入被配置为将边缘化时钟信号的频率移动与边界输入相关的恒定量; 比较第一比特流和第二比特流，并配置为检测与发送的比特流相关的第一比特流的错误; 以及接收机时钟信号或边缘时钟信号的计数周期，其中与被测接收机相关联的眼睛宽度与边缘输入，接收机时钟信号的频率以及当检测到错误时的时钟周期的计数有关。