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公开(公告)号：US20210152404A1
公开(公告)日：2021-05-20
申请号：US17127853
申请日：2020-12-18
Applicant: Intel Corporation
Inventor： Itamar Levin , Tali Warshavsky Grafi , Marco Cusmai , Ajay Balankutty , FNU Shiva Kiran , Ariel Cohen
IPC: H04L25/03
Abstract: An apparatus comprising at least one medium to transport a signal and an analog equalization circuit to perform equalization on the signal, wherein the analog equalization circuit comprises independently tunable parameters including a peak frequency gain and a mid-range frequency response slope.
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公开(公告)号：US20200321978A1
公开(公告)日：2020-10-08
申请号：US16905200
申请日：2020-06-18
Applicant: Intel Corporation
Inventor： Adee Ofir Ran , Amir Mezer , Alon Meisler , Assaf Benhamou , Itamar Levin , Yoni Landau
Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.
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公开(公告)号：US20190044763A1
公开(公告)日：2019-02-07
申请号：US15941071
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Nishantkumar Shah , Kevan A. Lillie , Adee Ofir Ran , Itamar Levin , Kent Lusted
Abstract: Technologies for cooperative link equalization include a network device with a network interface controller (NIC). The NIC is to monitor variation in a property of a link channel that connects the network device with a target network device. The NIC detects, based on the channel variation, an event that triggers a condition to change an equalization setting of the link channel. In response to the detection, the NIC communicates, via an in-band equalization control channel, changes to the equalization setting of the link channel to the target network device.
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公开(公告)号：US11134125B2
公开(公告)日：2021-09-28
申请号：US15749645
申请日：2016-09-23
Applicant: Intel Corporation
Inventor： Eliezer Tamir , Ben-Zion Friedman , Itamar Levin
IPC: H04L12/851 , H04L29/06 , H04L29/08 , H04L12/24 , H04L12/861 , H04L12/835 , H04L12/825 , H04L12/28
Abstract: Methods and apparatus for supporting active link status during LAN interface reset and reconfigurations. Under one aspect, during normal operations traffic is transmitted over an Ethernet link coupling a first link partner to a second link partner. In response to a network interface re-configuration event, transmission of traffic over the Ethernet link is paused while keeping the Physical layer (PHY) of the Ethernet link active. The configuration of the first link partner is updated while the transmission of traffic is paused and the PHY of the Ethernet link is active. Upon completion of the configuration update, the link partners resume transmission of traffic over the Ethernet link. Additional schemes are provided that support re-configuration of network interfaces that support link and per priority flow control. According to another aspect, separate power domains are used for the PHY and the MAC circuitry, enabling the MAC circuitry to be reset via a power cycle while maintaining power to the PHY circuitry.
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公开(公告)号：US20200326937A1
公开(公告)日：2020-10-15
申请号：US16912148
申请日：2020-06-25
Applicant: Intel Corporation
Inventor： Itamar Levin , Guilad Melzer , Alex Nayshtut , Raizy Kellerman
Abstract: The present disclosure provides privacy preservation of analytic workflows based on splitting the workflow into sub-workflows each with different privacy-preserving characteristics. Libraries are generated that provide for formatting and/or encrypting data for use in the sub-workflows and also for compiling a machine learning algorithm for the sub-workflows. Subsequently, the sub-workflows can be executed using the compiled algorithm and formatted data.
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Patent Agency Ranking
公开(公告)号：US10797855B2
公开(公告)日：2020-10-06
申请号：US16036227
申请日：2018-07-16
Applicant: INTEL CORPORATION
Inventor： Amir Laufer , Itamar Levin , Kevan A. Lillie
Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.
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公开(公告)号：US11567761B2
公开(公告)日：2023-01-31
申请号：US16912148
申请日：2020-06-25
Applicant: Intel Corporation
Inventor： Itamar Levin , Guilad Melzer , Alex Nayshtut , Raizy Kellerman
Abstract: The present disclosure provides privacy preservation of analytic workflows based on splitting the workflow into sub-workflows each with different privacy-preserving characteristics. Libraries are generated that provide for formatting and/or encrypting data for use in the sub-workflows and also for compiling a machine learning algorithm for the sub-workflows. Subsequently, the sub-workflows can be executed using the compiled algorithm and formatted data.
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公开(公告)号：US10924132B2
公开(公告)日：2021-02-16
申请号：US16324172
申请日：2017-09-08
Applicant: Intel Corporation
Inventor： Adee Ofir Ran , Amir Mezer , Alon Meisler , Assaf Benhamou , Itamar Levin , Yoni Landau
Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.
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公开(公告)号：US20190215008A1
公开(公告)日：2019-07-11
申请号：US16324172
申请日：2017-09-08
Applicant: Intel Corporation
Inventor： Adee Ofir Ran , Amir Mezer , Alon Meisler , Assaf Benhamou , Itamar Levin , Yoni Landau
CPC classification number: H03M13/015 , H03M13/09 , H03M13/13 , H03M13/15 , H03M13/1515 , H03M13/353 , H04L1/203
Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.
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公开(公告)号：US10027470B1
公开(公告)日：2018-07-17
申请号：US15393186
申请日：2016-12-28
Applicant: INTEL CORPORATION
Inventor： Amir Laufer , Itamar Levin , Kevan A. Lillie
Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.
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