公开(公告)号：US20230208437A1

公开(公告)日：2023-06-29

申请号：US17561246

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Sami Hyvonen ,  Fabrice Paillet ,  James Keith Hodgson ,  Anand Ramasundar ,  Cary Renzema ,  George Matthew ,  Sergio Carlo Rodriguez ,  Po-Cheng Chen ,  Sandeep Chilka ,  Bharadwaj Soundararajan

IPC: H03M7/16 ,  G05F1/46

CPC classification number: H03M7/165 ,  G05F1/46

Abstract: A digitally selectable power gate with thermometer-encoded upper bits may provide solutions for problems digital power gate-based regulators. These solutions may include the use of a fully binary power gate, either in structure or by local decoding of binary control signal to an addressable row-based power gate. This provides improved performance over a row-based code rotation, which is intended to avoid instantaneous overheating of power gate devices but may not mitigate aging effects. Another solution includes ganging a primary DLVR and one or more secondaries. The primary DLVR may include a voltage sense and active controller, which may forward its PG code to secondary instances. Therm and current sensor rotation may be performed locally at the secondaries and a current monitor data may be rolled up from all ganged DLVRs.