公开(公告)号：US20230205244A1

公开(公告)日：2023-06-29

申请号：US17561109

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Anand Ramasundar ,  Cary Renzema ,  Fabrice Paillet ,  James Keith Hodgson ,  Po-Cheng Chen ,  Sergio Carlo Rodriguez ,  Harish K. Krishnamurthy ,  Jason Muhlestein

IPC: G05F1/575 ,  G05F1/565

CPC classification number: G05F1/575 ,  G05F1/565

Abstract: An apparatus, system, and method for digital voltage regulator (DVR) control are provided. A DVR includes comparators configured to determine whether VLOAD drops below a gradual non-linear control (NLC) undershoot threshold voltage, rises above or drops below a reference voltage, and rises above a gradual NLC overshoot threshold voltage, respectively, power gates (PGs) configured to adjust VOUT based on a provided PG code; and VR controller circuitry comprising synchronous LC circuitry configured to increase or decrease, by a first increment, the PG code responsive to the VLOAD dropping below the reference voltage and rising above the reference voltage, and asynchronous gradual NLC circuitry configured to increase or decrease, by a second increment greater than the first increment and less than half a maximum PG code value, the PG code responsive to the VLOAD dropping below the gradual NLC undershoot threshold voltage and rising above the gradual NLC overshoot threshold voltage.

公开(公告)号：US20230168705A1

公开(公告)日：2023-06-01

申请号：US17540046

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Sergio Carlo Rodriguez ,  Cary D, Renzema ,  Amit K. Jain ,  Po-Cheng Chen ,  Fabrice Paillet ,  Anand Ramasundar ,  James Keith Hodgson

IPC: G05F1/577

CPC classification number: G05F1/577

Abstract: Embodiments herein relate to a feedback loop in a digital voltage regulator for controlling an output voltage. To avoid instability at light current loads, a gain of the loop is reduced as a power gate code indicates a reduced number of branches in set of current sources are enabled. In an example implementation, the code is classified into one range of a number of ranges, and the gain is set based on the one range. The gain can decrease each time the code enters a lower range, as indicated by the code crossing a threshold or predetermined value. For example, the gain can decrease by half each time the code enters a lower range.

公开(公告)号：US20230208437A1

公开(公告)日：2023-06-29

申请号：US17561246

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Sami Hyvonen ,  Fabrice Paillet ,  James Keith Hodgson ,  Anand Ramasundar ,  Cary Renzema ,  George Matthew ,  Sergio Carlo Rodriguez ,  Po-Cheng Chen ,  Sandeep Chilka ,  Bharadwaj Soundararajan

IPC: H03M7/16 ,  G05F1/46

CPC classification number: H03M7/165 ,  G05F1/46

Abstract: A digitally selectable power gate with thermometer-encoded upper bits may provide solutions for problems digital power gate-based regulators. These solutions may include the use of a fully binary power gate, either in structure or by local decoding of binary control signal to an addressable row-based power gate. This provides improved performance over a row-based code rotation, which is intended to avoid instantaneous overheating of power gate devices but may not mitigate aging effects. Another solution includes ganging a primary DLVR and one or more secondaries. The primary DLVR may include a voltage sense and active controller, which may forward its PG code to secondary instances. Therm and current sensor rotation may be performed locally at the secondaries and a current monitor data may be rolled up from all ganged DLVRs.