公开(公告)号：US11144027B2

公开(公告)日：2021-10-12

申请号：US16457929

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Giuseppe Capodanno ,  Jyotika A. Athavale ,  Riccardo Mariani

IPC: G06F11/00 ,  G05B19/042 ,  G06F11/07 ,  G06F11/14 ,  G05D1/00 ,  G05D1/02 ,  G11B20/18

Abstract: Soft error data describing soft errors predicted to affect at least a particular hardware component of a computing system are used to determine functional safety metric values. The computing system is to control at least a portion of physical functions of a machine using the particular hardware component. Respective soft error rates are determined for each of a set of classifications based on the soft errors described in the soft error data. Derating of the soft error rates are performed based on a set of one or more vulnerability factors to generate derated error rate values for each of the set of classifications. The functional safety metric value is determined from the derated error rate values to perform a functional safety analysis of the computing system.

公开(公告)号：US20190324422A1

公开(公告)日：2019-10-24

申请号：US16457929

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Giuseppe Capodanno ,  Jyotika A. Athavale ,  Riccardo Mariani

IPC: G05B19/042 ,  G06F11/07

Abstract: Soft error data describing soft errors predicted to affect at least a particular hardware component of a computing system are used to determine functional safety metric values. The computing system is to control at least a portion of physical functions of a machine using the particular hardware component. Respective soft error rates are determined for each of a set of classifications based on the soft errors described in the soft error data. Derating of the soft error rates are performed based on a set of one or more vulnerability factors to generate derated error rate values for each of the set of classifications. The functional safety metric value is determined from the derated error rate values to perform a functional safety analysis of the computing system.

公开(公告)号：US20220091917A1

公开(公告)日：2022-03-24

申请号：US17409343

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Alessandro Campinoti ,  Giuseppe Capodanno ,  Nabajit Deka ,  Prashanth R. Gadila ,  Elisa Spano

IPC: G06F11/07

Abstract: Techniques are disclosed for combining diagnostic features at different levels (with a special consideration of the application-oriented measures) though a quantitative analysis that provides evidence supporting a claimed diagnostic coverage (DC) calculation for circuits to meet defined functional safety standards. These techniques implement a parametrized approach to allow tuning by a system integrator according to its specific software application environment. The required safety level or DC goals may thus be attained based upon the results of the safety analysis (and failure rates) provided by a device manufacturer.

公开(公告)号：US11645140B2

公开(公告)日：2023-05-09

申请号：US17409343

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Alessandro Campinoti ,  Giuseppe Capodanno ,  Nabajit Deka ,  Prashanth R. Gadila ,  Elisa Spano

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/076

Abstract: Techniques are disclosed for combining diagnostic features at different levels (with a special consideration of the application-oriented measures) though a quantitative analysis that provides evidence supporting a claimed diagnostic coverage (DC) calculation for circuits to meet defined functional safety standards. These techniques implement a parametrized approach to allow tuning by a system integrator according to its specific software application environment. The required safety level or DC goals may thus be attained based upon the results of the safety analysis (and failure rates) provided by a device manufacturer.