公开(公告)号：US11520297B2

公开(公告)日：2022-12-06

申请号：US16370461

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Rajesh Banginwar ,  Ramkumar Jayaraman ,  Nabajit Deka ,  Riccardo Mariani

IPC: G06F13/40 ,  G05B9/02 ,  H04L12/40 ,  G06F9/54 ,  G06F11/30

Abstract: Methods and apparatus relating to enhancing diagnostic capabilities of computing systems by combining variable patrolling Application Program Interface (API) and comparison mechanism of variables are described. In one embodiment, a first processor core executes a first instance of a workload to generate a first set of safety variables. A second processor core executes a second instance of the workload to generate a second set of safety variables. A third processor core generates a signal in response to comparison of the first set of safety variables and the second set of safety variables. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190235448A1

公开(公告)日：2019-08-01

申请号：US16370461

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Rajesh Banginwar ,  Ramkumar Jayaraman ,  Nabajit Deka ,  Riccardo Mariani

IPC: G05B9/02 ,  H04L12/40 ,  G06F13/40 ,  G06F9/54

CPC classification number: G05B9/02 ,  G06F9/541 ,  G06F13/4022 ,  G06F2213/0016 ,  G06F2213/0026 ,  G06F2213/0038 ,  H04L12/40 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: Methods and apparatus relating to enhancing diagnostic capabilities of computing systems by combining variable patrolling Application Program Interface (API) and comparison mechanism of variables are described. In one embodiment, a first processor core executes a first instance of a workload to generate a first set of safety variables. A second processor core executes a second instance of the workload to generate a second set of safety variables. A third processor core generates a signal in response to comparison of the first set of safety variables and the second set of safety variables. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190049916A1

公开(公告)日：2019-02-14

申请号：US16155495

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Rajesh Banginwar ,  Wenjun Zhang

IPC: G05B19/042

Abstract: An apparatus of a System on Chip (SoC) to implement a one out of two diagnostics (1oo2D) safety system comprises a memory comprising firmware to provide monitoring of the SoC and a second SoC, and a communication interface to provide cross-monitoring between the SoC and the second SoC. The firmware and the communication interface enable the SoC and the second SoC to implement the 1oo2D safety system without significant hardware or software external to the SoC.

公开(公告)号：US11645140B2

公开(公告)日：2023-05-09

申请号：US17409343

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Alessandro Campinoti ,  Giuseppe Capodanno ,  Nabajit Deka ,  Prashanth R. Gadila ,  Elisa Spano

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/076

Abstract: Techniques are disclosed for combining diagnostic features at different levels (with a special consideration of the application-oriented measures) though a quantitative analysis that provides evidence supporting a claimed diagnostic coverage (DC) calculation for circuits to meet defined functional safety standards. These techniques implement a parametrized approach to allow tuning by a system integrator according to its specific software application environment. The required safety level or DC goals may thus be attained based upon the results of the safety analysis (and failure rates) provided by a device manufacturer.

公开(公告)号：US11360846B2

公开(公告)日：2022-06-14

申请号：US16585104

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Gabriele Boschi ,  Roger May ,  Gabriele Paoloni ,  Nabajit Deka ,  Matteo Salardi

IPC: G06F11/20 ,  G06F11/07 ,  G06F11/18 ,  G06F11/16

Abstract: Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.

公开(公告)号：US11841776B2

公开(公告)日：2023-12-12

申请号：US16439407

申请日：2019-06-12

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Roger May ,  Prashanth Gadila

IPC: G06F11/00 ,  G06F11/16 ,  G05B9/02 ,  G06F11/30 ,  G06F13/12 ,  G06F11/07

CPC classification number: G06F11/1641 ,  G05B9/02 ,  G06F11/0796 ,  G06F11/3055 ,  G06F13/122

Abstract: Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.

公开(公告)号：US20220091917A1

公开(公告)日：2022-03-24

申请号：US17409343

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Alessandro Campinoti ,  Giuseppe Capodanno ,  Nabajit Deka ,  Prashanth R. Gadila ,  Elisa Spano

IPC: G06F11/07

Abstract: Techniques are disclosed for combining diagnostic features at different levels (with a special consideration of the application-oriented measures) though a quantitative analysis that provides evidence supporting a claimed diagnostic coverage (DC) calculation for circuits to meet defined functional safety standards. These techniques implement a parametrized approach to allow tuning by a system integrator according to its specific software application environment. The required safety level or DC goals may thus be attained based upon the results of the safety analysis (and failure rates) provided by a device manufacturer.

公开(公告)号：US10955805B2

公开(公告)日：2021-03-23

申请号：US16155495

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Rajesh Banginwar ,  Wenjun Zhang

IPC: G06F11/00 ,  G05B19/042 ,  G06F11/07

Abstract: An apparatus of a System on Chip (SoC) to implement a one out of two diagnostics (1oo2D) safety system comprises a memory comprising firmware to provide monitoring of the SoC and a second SoC, and a communication interface to provide cross-monitoring between the SoC and the second SoC. The firmware and the communication interface enable the SoC and the second SoC to implement the 1oo2D safety system without significant hardware or software external to the SoC.

公开(公告)号：US20190294125A1

公开(公告)日：2019-09-26

申请号：US16439407

申请日：2019-06-12

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Roger May ,  Prashanth Gadila

IPC: G05B9/02 ,  G06F13/12 ,  G06F11/30

Abstract: Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.