公开(公告)号：US20220091917A1

公开(公告)日：2022-03-24

申请号：US17409343

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Alessandro Campinoti ,  Giuseppe Capodanno ,  Nabajit Deka ,  Prashanth R. Gadila ,  Elisa Spano

IPC: G06F11/07

Abstract: Techniques are disclosed for combining diagnostic features at different levels (with a special consideration of the application-oriented measures) though a quantitative analysis that provides evidence supporting a claimed diagnostic coverage (DC) calculation for circuits to meet defined functional safety standards. These techniques implement a parametrized approach to allow tuning by a system integrator according to its specific software application environment. The required safety level or DC goals may thus be attained based upon the results of the safety analysis (and failure rates) provided by a device manufacturer.

公开(公告)号：US11645140B2

公开(公告)日：2023-05-09

申请号：US17409343

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Alessandro Campinoti ,  Giuseppe Capodanno ,  Nabajit Deka ,  Prashanth R. Gadila ,  Elisa Spano

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/076

Abstract: Techniques are disclosed for combining diagnostic features at different levels (with a special consideration of the application-oriented measures) though a quantitative analysis that provides evidence supporting a claimed diagnostic coverage (DC) calculation for circuits to meet defined functional safety standards. These techniques implement a parametrized approach to allow tuning by a system integrator according to its specific software application environment. The required safety level or DC goals may thus be attained based upon the results of the safety analysis (and failure rates) provided by a device manufacturer.