公开(公告)号：US20200350028A1

公开(公告)日：2020-11-05

申请号：US16852162

申请日：2020-04-17

Applicant: Intel Corporation

Inventor： HAN ZHAO ,  PRANAV KALAVADE ,  KRISHNA K. PARAT

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

公开(公告)号：US20190043594A1

公开(公告)日：2019-02-07

申请号：US15831984

申请日：2017-12-05

Applicant: Intel Corporation

Inventor： HAN ZHAO ,  PRANAV KALAVADE ,  KRISHNA K. PARAT

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.