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公开(公告)号：US12003352B2
公开(公告)日：2024-06-04
申请号：US17029445
申请日：2020-09-23
Applicant: Intel Corporation
Inventor： Peng Li , Masashi Shimanouchi , Hsinho Wu
CPC classification number: H04L25/03031 , H03M1/1215 , H04B10/541 , H04B10/6971 , H04L25/03267 , H04L27/01 , H04L2025/0349
Abstract: A method facilitates determining transmission loss in a transmission signal and adjusting a receiver setting of a receiver to compensate for the transmission loss. The method includes transmitting a transmission signal from a transmitter and receiving the transmission signal by a first receiver and a second receiver. The method includes digitizing the transmission signal by the first receiver at a first sampling frequency and digitizing the transmission signal by the second receiver at a second sampling frequency that is less than or equal to the first sampling frequency. The method includes generating a PAM-n eye diagram of the transmission signal by the second receiver using digitized signals digitized by the first and second receivers and adjusting an equalizer setting of a first equalizer of the first receiver using eye-opening information of the PAM-n eye diagram where the eye-opening information includes information for the transmission loss.
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公开(公告)号：US10530614B2
公开(公告)日：2020-01-07
申请号：US16230974
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Hsinho Wu , Masashi Shimanouchi , Peng Li
Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.
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公开(公告)号：US11356303B2
公开(公告)日：2022-06-07
申请号：US17214171
申请日：2021-03-26
Applicant: Intel Corporation
Inventor： Hsinho Wu , Masashi Shimanouchi , Peng Li
Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.
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公开(公告)号：US20210218603A1
公开(公告)日：2021-07-15
申请号：US17214171
申请日：2021-03-26
Applicant: Intel Corporation
Inventor： Hsinho Wu , Masashi Shimanouchi , Peng Li
Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.
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公开(公告)号：US10965501B2
公开(公告)日：2021-03-30
申请号：US16736436
申请日：2020-01-07
Applicant: Intel Corporation
Inventor： Hsinho Wu , Masashi Shimanouchi , Peng Li
Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.
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Patent Agency Ranking
公开(公告)号：US10476716B2
公开(公告)日：2019-11-12
申请号：US16029900
申请日：2018-07-09
Applicant: Intel Corporation
Inventor： Mike Peng Li , Hsinho Wu , Masashi Shimanouchi
Abstract: A method includes receiving an n-level Pulse Amplitude Modulated (PAM-n) signal at a receiver from a transmitter via a channel. The method also includes determining one or more sampling times of the PAM-n signal. The method further includes determining one or more slicing levels of the PAM-n signal. The method also includes extracting and decomposing jitter in the PAM-n signal for each slicing level of the PAM-n signal to determine one or more jitter components. The method further includes extracting and decomposing noise in the PAM-n signal for each data level of the PAM-n signal to determine one or more noise components. The method also includes adjusting the receiver, the transmitter, the channel, or any combination thereof, based on the one or more jitter components, the one or more noise components, or both.
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公开(公告)号：US20180316527A1
公开(公告)日：2018-11-01
申请号：US16029900
申请日：2018-07-09
Applicant: Intel Corporation
Inventor： Mike Peng Li , Hsinho Wu , Masashi Shimanouchi
Abstract: A method includes receiving an n-level Pulse Amplitude Modulated (PAM-n) signal at a receiver from a transmitter via a channel. The method also includes determining one or more sampling times of the PAM-n signal. The method further includes determining one or more slicing levels of the PAM-n signal. The method also includes extracting and decomposing jitter in the PAM-n signal for each slicing level of the PAM-n signal to determine one or more jitter components. The method further includes extracting and decomposing noise in the PAM-n signal for each data level of the PAM-n signal to determine one or more noise components. The method also includes adjusting the receiver, the transmitter, the channel, or any combination thereof, based on the one or more jitter components, the one or more noise components, or both.
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公开(公告)号：US20210006439A1
公开(公告)日：2021-01-07
申请号：US17029445
申请日：2020-09-23
Applicant: Intel Corporation
Inventor： Peng Li , Masashi Shimanouchi , Hsinho Wu
Abstract: A method facilitates determining transmission loss in a transmission signal and adjusting a receiver setting of a receiver to compensate for the transmission loss. The method includes transmitting a transmission signal from a transmitter and receiving the transmission signal by a first receiver and a second receiver. The method includes digitizing the transmission signal by the first receiver at a first sampling frequency and digitizing the transmission signal by the second receiver at a second sampling frequency that is less than or equal to the first sampling frequency. The method includes generating a PAM-n eye diagram of the transmission signal by the second receiver using digitized signals digitized by the first and second receivers and adjusting an equalizer setting of a first equalizer of the first receiver using eye-opening information of the PAM-n eye diagram where the eye-opening information includes information for the transmission loss.
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公开(公告)号：US20190132160A1
公开(公告)日：2019-05-02
申请号：US16230974
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Hsinho Wu , Masashi Shimanouchi , Peng Li
IPC: H04L25/03
Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.
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公开(公告)号：US10020967B1
公开(公告)日：2018-07-10
申请号：US15443791
申请日：2017-02-27
Applicant: Intel Corporation
Inventor： Mike Peng Li , Hsinho Wu , Masashi Shimanouchi
CPC classification number: H04L27/06 , H04L1/00 , H04L1/205 , H04L25/03031 , H04L25/061 , H04L27/04
Abstract: A method includes receiving an n-level Pulse Amplitude Modulated (PAM-n) signal at a receiver from a transmitter via a channel. The method also includes determining one or more sampling times of the PAM-n signal. The method further includes determining one or more slicing levels of the PAM-n signal. The method also includes extracting and decomposing jitter in the PAM-n signal for each slicing level of the PAM-n signal to determine one or more jitter components. The method further includes extracting and decomposing noise in the PAM-n signal for each data level of the PAM-n signal to determine one or more noise components. The method also includes adjusting the receiver, the transmitter, the channel, or any combination thereof, based on the one or more jitter components, the one or more noise components, or both.
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