公开(公告)号：US20200379835A1

公开(公告)日：2020-12-03

申请号：US16994269

申请日：2020-08-14

Applicant: Intel Corporation

Inventor： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

IPC: G06F11/07 ,  G06F12/08 ,  G06F9/30

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

公开(公告)号：US09892481B2

公开(公告)日：2018-02-13

申请号：US15278316

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Boris Ginzburg ,  Esfirush Natanzon ,  Ilya Osadchiy ,  Yoav Zach

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

公开(公告)号：US20190205200A1

公开(公告)日：2019-07-04

申请号：US16234539

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

IPC: G06F11/07 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F11/0784 ,  G06F9/30036 ,  G06F9/30043 ,  G06F12/08

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

公开(公告)号：US10255126B2

公开(公告)日：2019-04-09

申请号：US15893982

申请日：2018-02-12

Applicant: Intel Corporation

Inventor： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

IPC: G06F9/30 ,  G06F11/07 ,  G06F12/08

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

公开(公告)号：US11275637B2

公开(公告)日：2022-03-15

申请号：US16994269

申请日：2020-08-14

Applicant: Intel Corporation

Inventor： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

IPC: G06F11/07 ,  G06F12/08 ,  G06F9/30

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

公开(公告)号：US20170018051A1

公开(公告)日：2017-01-19

申请号：US15278316

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Boris Ginzburg ,  Esfir Natanzon ,  Ilya Osadchiy ,  Yoav Zach

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

Abstract translation: 可以使用一个处理器上的线程来使另一个处理器能够锁定或释放互斥体。 例如，图形处理单元可以使用中央处理单元线程来保护用于共享存储器的互斥体。