-
公开(公告)号：US20200218568A1
公开(公告)日：2020-07-09
申请号：US16729760
申请日：2019-12-30
Applicant: Intel Corporation
Inventor： Ronny Ronen , Boris Ginzburg , Eliezer Weissmann
IPC: G06F9/48 , G06F9/38 , G06F15/78 , G06F12/1027
Abstract: An apparatus is described having multiple cores, each core having: a) a CPU; b) an accelerator; and, c) a controller and a plurality of order buffers coupled between the CPU and the accelerator. Each of the order buffers is dedicated to a different one of the CPU's threads. Each one of the order buffers is to hold one or more requests issued to the accelerator from its corresponding thread. The controller is to control issuance of the order buffers' respective requests to the accelerator.
-
公开(公告)号：US10120691B2
公开(公告)日：2018-11-06
申请号：US15214270
申请日：2016-07-19
Applicant: Intel Corporation
Inventor： Boris Ginzburg , Ronny Ronen , Eliezer Weissmann , Karthikeyan Vaithianathan , Ehud Cohen
Abstract: In one embodiment, a processor includes an accelerator, a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction, and an execution unit to execute the first decoded instruction to, for a thread executing on the accelerator that is to be placed in an inactive state, cause a save of context information for the thread, and a save of a vector identifying the accelerator corresponding to the context information, and execute the second decoded instruction to read the vector to determine the accelerator to restore saved context information into for the thread, read the saved context information, and restore the saved context information into the accelerator.
-
公开(公告)号：US11243768B2
公开(公告)日：2022-02-08
申请号：US16259880
申请日：2019-01-28
Applicant: Intel Corporation
Inventor： Efraim Rotem , Eliezer Weissmann , Boris Ginzburg , Alon Naveh , Nadav Shulman , Ronny Ronen
Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.
-
公开(公告)号：US20190155606A1
公开(公告)日：2019-05-23
申请号：US16259880
申请日：2019-01-28
Applicant: Intel Corporation
Inventor： Efraim Rotem , Eliezer Weissmann , Boris Ginzburg , Alon Naveh , Nadav Shulman , Ronny Ronen
IPC: G06F9/30 , G06F9/455 , G06F9/38 , G06F11/34 , G06F1/3234
Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.
-
5.发明授权公开(公告)号：US09971688B2
公开(公告)日：2018-05-15
申请号：US15394539
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Karthikeyan Karthik Vaithianathan , Yoav Zach , Boris Ginzburg , Ronny Ronen
IPC: G06F12/00 , G06F12/0811 , G06F12/1027 , G06F12/1009 , G06F3/06 , G06F12/02
CPC classification number: G06F12/0811 , G06F3/0646 , G06F3/0662 , G06F3/0668 , G06F9/3851 , G06F9/3881 , G06F9/3887 , G06F12/0292 , G06F12/084 , G06F12/0875 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F12/1072 , G06F12/1081 , G06F12/1441 , G06F12/145 , G06F2212/1024 , G06F2212/283 , G06F2212/302 , G06F2212/452 , G06F2212/60 , G06F2212/62 , G06F2212/65 , G06F2212/68 , G06F2212/683 , G06F2212/684
Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
-
Patent Agency Ranking
公开(公告)号：US20190205200A1
公开(公告)日：2019-07-04
申请号：US16234539
申请日：2018-12-27
Applicant: Intel Corporation
Inventor： Boris Ginzburg , Ronny Ronen , Ilya Osadchiy
CPC classification number: G06F11/0784 , G06F9/30036 , G06F9/30043 , G06F12/08
Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.
-
公开(公告)号：US10255126B2
公开(公告)日：2019-04-09
申请号：US15893982
申请日：2018-02-12
Applicant: Intel Corporation
Inventor： Boris Ginzburg , Ronny Ronen , Ilya Osadchiy
Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.
-
公开(公告)号：US11275637B2
公开(公告)日：2022-03-15
申请号：US16994269
申请日：2020-08-14
Applicant: Intel Corporation
Inventor： Boris Ginzburg , Ronny Ronen , Ilya Osadchiy
Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.
-
9.发明授权公开(公告)号：US10078519B2
公开(公告)日：2018-09-18
申请号：US15221557
申请日：2016-07-27
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Karthikeyan Karthik Vaithianathan , Yoav Zach , Boris Ginzburg , Ronny Ronen
IPC: G06F12/10 , G06F9/38 , G06F12/1027 , G06F12/1081 , G06F12/1072 , G06F12/0875 , G06F12/1009
CPC classification number: G06F9/3851 , G06F3/0646 , G06F3/0662 , G06F3/0668 , G06F9/3881 , G06F9/3887 , G06F12/0292 , G06F12/0811 , G06F12/084 , G06F12/0875 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F12/1072 , G06F12/1081 , G06F12/1441 , G06F12/145 , G06F2212/1024 , G06F2212/283 , G06F2212/302 , G06F2212/452 , G06F2212/60 , G06F2212/62 , G06F2212/65 , G06F2212/68 , G06F2212/683 , G06F2212/684
Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
-
公开(公告)号：US20200379835A1
公开(公告)日：2020-12-03
申请号：US16994269
申请日：2020-08-14
Applicant: Intel Corporation
Inventor： Boris Ginzburg , Ronny Ronen , Ilya Osadchiy
Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.016 seconds)
