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    CONTROLLING POWER STATE DEMOTION IN A PROCESSOR
    3.
    发明申请
    CONTROLLING POWER STATE DEMOTION IN A PROCESSOR 审中-公开

    公开(公告)号：US20200210184A1

    公开(公告)日：2020-07-02

    申请号：US16233297

    申请日：2018-12-27

    Applicant: Intel Corporation

    Inventor： Eliezer Weissmann ,  Hisham Abu-Salah ,  Daniel Lederman ,  Nir Rosenzweig ,  Efraim Rotem ,  Esfir Natanzon ,  Yevgeni Sabin ,  Shay Levy

    IPC: G06F9/30 ,  G06F1/3234 ,  G06F1/329

    Abstract: In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.

    Providing Lifetime Statistical Information For A Processor
    4.
    发明申请
    Providing Lifetime Statistical Information For A Processor 有权
    为处理器提供终身统计信息

    公开(公告)号：US20160070321A1

    公开(公告)日：2016-03-10

    申请号：US14482148

    申请日：2014-09-10

    Applicant: Intel Corporation

    Inventor： Dorit Shapira ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Esfir Natanzon ,  Nir Rosenzweig

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

    Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括多个核和耦合到核的功率控制单元（PCU）。 PCU具有应力检测器，用于接收处理器运行的电压和温度，并计算包括有效可靠性压力在内的寿命统计信息，在诸如个人计算机，服务器计算机等计算系统的多个引导周期之后维持寿命统计信息， 平板电脑，智能电话或任何其他计算平台，基于生存期统计信息来控制处理器的一个或多个操作参数，并且经由接口将至少一部分生命周期统计信息传达给用户和/或管理实体 的处理器。 描述和要求保护其他实施例。

    Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation
    8.
    发明授权
    Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation 有权
    使用动态部分二进制翻译实现高性能ISA虚拟化的方法和装置

    公开(公告)号：US09552207B2

    公开(公告)日：2017-01-24

    申请号：US15013993

    申请日：2016-02-02

    Applicant: Intel Corporation

    Inventor： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

    IPC: G06F9/30 ,  G06F9/45 ,  G06F9/455 ,  G06F12/08

    CPC classification number: G06F9/30181 ,  G06F8/52 ,  G06F9/30145 ,  G06F9/45558 ,  G06F9/467 ,  G06F12/0875 ,  G06F2212/452

    Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.

    Abstract translation: 公开了用于本地指令集的虚拟化的方法，装置和系统。 实施例包括执行本地指令的处理器核心和第二核心，或者替代地，只有第二处理器核心在执行排除本地指令集的部分的第二指令集时消耗较少的功率。 第二核心解码器检测第二指令集的无效操作码。 微码层拆解器确定是否应翻译操作码。 翻译运行时环境识别包含第二指令集的无效操作码，其他无效操作码和中间有效操作码的可执行区域。 分析单元在执行无效操作码之前确定初始机器状态。 生成可执行区域的部分翻译，其中包括无效操作码的翻译和机器状态的状态恢复的封装，并将其保存到翻译高速缓冲存储器。

    CONTROLLING A GUARANTEED FREQUENCY OF A PROCESSOR
    10.
    发明申请
    CONTROLLING A GUARANTEED FREQUENCY OF A PROCESSOR 有权
    控制处理器的保证频率

    公开(公告)号：US20160147275A1

    公开(公告)日：2016-05-26

    申请号：US14554628

    申请日：2014-11-26

    Applicant: Intel Corporation

    Inventor： Eliezer Weissmann ,  Hisham Abu Salah ,  Efraim Rotem ,  Guy M. Therien ,  Nadav Shulman ,  Esfir Natanzon ,  Paul S. Diefenbaugh

    IPC: G06F1/32 ,  G06F1/20

    CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括用于执行指令的一个或多个核和耦合到所述一个或多个核的功率控制器。 反过来，功率控制器包括控制逻辑，用于从一个或多个源接收动态变化到一个或多个核中的至少一个运行的保证频率的指示，以及确定最终保证 处理器要为下一个窗口操作的频率，以及将最终保证频率传送到至少一个实体。 描述和要求保护其他实施例。

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