公开(公告)号：US12149207B2

公开(公告)日：2024-11-19

申请号：US17323189

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Ofir Degani ,  Assaf Ben-Bassat ,  Ashoke Ravi ,  Ina Shternberg ,  Naor Shay

IPC: H03F1/02 ,  H03F3/21

Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

公开(公告)号：US20220376657A1

公开(公告)日：2022-11-24

申请号：US17323189

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Ofir Degani ,  Assaf Ben-Bassat ,  Ashoke Ravi ,  Ina Shternberg ,  Naor Shay

IPC: H03F1/02 ,  H03F3/21

Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

公开(公告)号：US20230179251A1

公开(公告)日：2023-06-08

申请号：US17997663

申请日：2020-06-02

Applicant: Intel Corporation

Inventor： Assaf Ben-bassat ,  Ofir Degani ,  Anna Nazimov ,  Naor Shay ,  Ina Shternberg

IPC: H04B1/40 ,  H03K19/0948 ,  H03K19/20 ,  H03M1/66

CPC classification number: H04B1/40 ,  H03K19/0948 ,  H03K19/20 ,  H03M1/66

Abstract: Techniques are described to address P-MOS bias temperature instability (BTI) stress issues within capacitive radio frequency digital-to-analog converter (CDAC) using a circuit architecture solution that functions to protect the transistors in various operating conditions. Techniques are disclosed that function to float one or both of the negative and positive power supply rail voltages higher or lower, respectively, for CDAC cells depending upon various operating scenarios. These scenarios include the transmitting state of individual CDAC cells and the transmitting state of the CDAC array in which the CDAC cell is implemented.