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公开(公告)号：US12130651B2
公开(公告)日：2024-10-29
申请号：US17822266
申请日：2022-08-25
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Renald Boulestin
IPC: H03M1/66 , G05F3/26 , H01L27/088 , H01L29/423
CPC classification number: G05F3/262 , H01L27/088 , H01L29/42376 , H03M1/66
Abstract: A current mirror circuit includes a first MOS-type transistor and a second MOS-type transistor assembled as a current mirror, wherein the first transistor has a first gate length different from a second gate length of the second transistor.
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公开(公告)号：US12119835B2
公开(公告)日：2024-10-15
申请号：US17964031
申请日：2022-10-11
Inventor： Ahmed Elkholy , Jun Cao , Adesh Garg
CPC classification number: H03M1/0626 , H03M1/066 , H03M1/0665 , H03M1/0673 , H03M1/66
Abstract: A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.
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公开(公告)号：US12094527B2
公开(公告)日：2024-09-17
申请号：US17709794
申请日：2022-03-31
Applicant: International Business Machines Corporation
Inventor： Rajiv Joshi , Sudipto Chakraborty
IPC: G11C11/412 , G06N3/065 , G11C11/418 , G11C11/419 , H03M1/66
CPC classification number: G11C11/418 , G06N3/065 , G11C11/412 , G11C11/419 , H03M1/66
Abstract: An apparatus includes a memory array. The array in turn includes a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, coupled to the plurality of word lines and the plurality of bit line pairs, and located at the plurality of cell locations. A plurality of word line drivers are coupled to the plurality of word lines, a dynamic voltage boost is coupled to the memory array, and a controller is coupled to the plurality of word line drivers and the dynamic voltage boost. The controller is configured to cause the dynamic voltage boost to boost the cells during a multiply accumulate operation.
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公开(公告)号：US12092688B2
公开(公告)日：2024-09-17
申请号：US17733377
申请日：2022-04-29
Applicant: Advantest Corporation
Inventor： Andreas Beermann , Martin Mücke
IPC: G01R31/317 , G01R31/319 , H03M1/06 , H03M1/66 , H04L7/00
CPC classification number: G01R31/31727 , G01R31/31726 , G01R31/31917 , H03M1/0624 , H03M1/66 , H04L7/0012
Abstract: The invention concerns a circuit for transferring a data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal synchronized with a source clock signal, and to receive such data by sampling the data signal synchronized with a target clock signal; a phase comparator which is configured to determine a phase relationship between the source clock signal and the target clock signal; and a data signal synchronization circuit configured to receive data signal transitions that are synchronized with the source clock signal, and to provide a synchronized data signal transitions of which are synchronized with the target clock signal.
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公开(公告)号：US12088331B2
公开(公告)日：2024-09-10
申请号：US18157851
申请日：2023-01-23
Applicant: RDA MICROELECTRONICS (BEIJING) CO., LTD.
CPC classification number: H04B1/0475 , H03M1/66 , H04B2001/0416
Abstract: Embodiments of the present disclosure provide a signal transmitting method. According to the method, in a signal transmitting process, before entering a digital to analog converter (DAC), a first frequency modulated signal of a high-pass channel is first subjected to nonlinear compensation and gain mismatch compensation. In the process, a nonlinear compensation coefficient and a gain mismatch compensation coefficient are determined according to an output voltage of the high-pass channel and an output frequency of a voltage-controlled oscillator (VCO) during a calibration stage.
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Patent Agency Ranking
公开(公告)号：US20240255981A1
公开(公告)日：2024-08-01
申请号：US18629559
申请日：2024-04-08
Inventor： Qiaonian YU , Zhenxing ZHANG , Xiong XU , Shengyu ZHANG
Abstract: In a waveform data transmission method, control and measurement waveform data of a first signal waveform for control and measurement of a quantum chip is generated by control and measurement software of a qubit control and measurement system. The control and measurement waveform data is compressed, by the control and measurement software, to obtain compressed control and measurement waveform data. The compressed control and measurement waveform data is transmitted to an electronics system of the qubit control and measurement system. The compressed control and measurement waveform data is decompressed, by processing circuitry of the electronics system, to obtain recovered control and measurement waveform data. The first signal waveform is transmitted to the quantum chip according to the recovered control and measurement waveform data.
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公开(公告)号：US12052024B2
公开(公告)日：2024-07-30
申请号：US17871683
申请日：2022-07-22
Applicant: Apple Inc.
Inventor： Filipe Tabarani , Timo W Gossmann
CPC classification number: H03M1/002 , H03M1/0648 , H04L27/206 , H04L27/362 , H03M1/66
Abstract: The current disclosure is related to a column and line digital-to-analog converter (DAC) with a hybrid coupler for generating quadrature analog signals. The DAC may include an array of unit power amplifiers (cells). A first portion of the cells of the array may be coupled to a first column decoder to receive in-phase components of digital signals and a second portion of the cells may be coupled to a second column decoder to receive quadrature components of the digital signals. The first portion of the cells of the array may generate in-phase components of analog signals and the second portion of the cells of the array may generate quadrature components of the analog signals. A hybrid coupler of the DAC may receive the in-phase and quadrature components of the analog signals with a similar phase, delay the quadrature components by a phase delay (e.g., 90 degrees), and output the resulting analog signals.
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公开(公告)号：US12046251B2
公开(公告)日：2024-07-23
申请号：US17637818
申请日：2019-11-10
Applicant: AMICRO SEMICONDUCTOR CO., LTD.
Inventor： Lili Wang
CPC classification number: G10L21/02 , H03M1/0626 , H03M1/66
Abstract: An interpolation filtering system implemented by a digital circuit is provided, it includes an interpolation filtering operation controller, a cascaded drive module, an intermediate result cache Random Access Memory (RAM), and a filter coefficient storage Read Only Memory (ROM). The intermediate result cache RAM is configured to store externally input data of the interpolation filtering system and intermediate results output by the filter operation modules. The filter coefficient storage ROM is configured to store filter coefficients required for calculation by the filter operation modules. The interpolation filtering operation controller is configured to control, under the drive of counting beats output by the cascaded drive module, the master state machine to select data of the intermediate result cache TAM or externally directly input data to be sent to the cascaded filter operation modules for accumulation operation, and to select the filter coefficients of the filter coefficient storage ROM for multiplication operation.
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公开(公告)号：US12028086B2
公开(公告)日：2024-07-02
申请号：US17819092
申请日：2022-08-11
Applicant: NXP USA, INC.
Inventor： Yizhong Zhang , Jie Jin , Stefano Pietri , Michael Todd Berens , Hongyan Yao , Jiawei Fu
CPC classification number: H03M1/1057 , H03M1/66 , H03M1/687 , H03M1/765 , H03M1/785
Abstract: A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fL based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fL with a high frequency clock having a constant frequency fH. A memory is included to store at least two counter values generating by comparing fL and fH once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.
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公开(公告)号：US12025646B2
公开(公告)日：2024-07-02
申请号：US17649887
申请日：2022-02-03
Applicant: SigmaSense, LLC.
Inventor： Phuong Huynh , Patrick Troy Gray
CPC classification number: G01R29/26 , G01R31/40 , H03F3/45475 , H03K5/1252 , H03K5/24 , H03F2200/129 , H03F2203/45116 , H03K2005/00078 , H03M1/12 , H03M1/66
Abstract: A method includes providing, by a signal source circuit of a sensing circuit, a signal to a sensor via a conductor. When the sensor is exposed to a condition and is receiving the signal, an electrical characteristic of the sensor affects the signal. The signal includes at least one of: a direct current (DC) component and an oscillating component. When the sensing circuit is in a noisy environment, transient noise couples with the signal to produce a noisy signal. The method further includes comparing, by a transient circuit of the sensing circuit, the noisy signal with a representation of the noisy signal. When the noisy signal compares unfavorably with the representation of the noisy signal, supplying, by the transient circuit, a compensation signal to the conductor. A level of the compensation signal corresponds to a level at which the noisy signal compares unfavorably with the representation of the noisy signal.
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