公开(公告)号：US20220376657A1

公开(公告)日：2022-11-24

申请号：US17323189

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Ofir Degani ,  Assaf Ben-Bassat ,  Ashoke Ravi ,  Ina Shternberg ,  Naor Shay

IPC: H03F1/02 ,  H03F3/21

Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

公开(公告)号：US20230179251A1

公开(公告)日：2023-06-08

申请号：US17997663

申请日：2020-06-02

Applicant: Intel Corporation

Inventor： Assaf Ben-bassat ,  Ofir Degani ,  Anna Nazimov ,  Naor Shay ,  Ina Shternberg

IPC: H04B1/40 ,  H03K19/0948 ,  H03K19/20 ,  H03M1/66

CPC classification number: H04B1/40 ,  H03K19/0948 ,  H03K19/20 ,  H03M1/66

Abstract: Techniques are described to address P-MOS bias temperature instability (BTI) stress issues within capacitive radio frequency digital-to-analog converter (CDAC) using a circuit architecture solution that functions to protect the transistors in various operating conditions. Techniques are disclosed that function to float one or both of the negative and positive power supply rail voltages higher or lower, respectively, for CDAC cells depending upon various operating scenarios. These scenarios include the transmitting state of individual CDAC cells and the transmitting state of the CDAC array in which the CDAC cell is implemented.

公开(公告)号：US12149207B2

公开(公告)日：2024-11-19

申请号：US17323189

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Ofir Degani ,  Assaf Ben-Bassat ,  Ashoke Ravi ,  Ina Shternberg ,  Naor Shay

IPC: H03F1/02 ,  H03F3/21

Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

公开(公告)号：US20220416736A1

公开(公告)日：2022-12-29

申请号：US17359187

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： David Ben-Haim ,  Ofir Degani ,  Assaf Ben-Bassat ,  Anna Nazimov ,  Naor Shay

IPC: H03F3/24 ,  H03F3/60 ,  H03F3/189

Abstract: Various embodiments provide systems, devices, and methods for a multi-core digital power amplifier with an unbalanced power combiner. In one example, two or more cores are combined with a transformer section that has a first coupling coefficient and another two or more cores are combined with a second transformer section that has a second coupling coefficient that is different than the first coupling coefficient. The outputs of different cores may be cross-coupled with the primary inductors of the transformers. The digital power amplifier may provide an output power that is flat over a relatively wide operating range. Other embodiments may be described and claimed.