公开(公告)号：US20200098159A1

公开(公告)日：2020-03-26

申请号：US16142692

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： JOHN GIERACH

IPC: G06T15/00 ,  G06T15/80

Abstract: Embodiments described herein provide an apparatus comprising a processor to maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse selection dispatch rate, receive a request message to dispatch coarse compute shader work, the request message comprising a requested coarse selection dispatch rate and a thread identifier, and store the request message in a FIFO queue structure having a coarse selection dispatch rate corresponding to the requested coarse selection dispatch rate associated with the request message. Other embodiments may be described and claimed.

公开(公告)号：US20200175741A1

公开(公告)日：2020-06-04

申请号：US16208632

申请日：2018-12-04

Applicant: Intel Corporation

Inventor： JOHN GIERACH ,  SRIVIDYA A. KARUMURI ,  THOMAS RAOUX ,  DEVAN BURKE ,  WOJTEK RAJSKI ,  JEREMY BRENNAN

IPC: G06T15/00 ,  G06T1/20

Abstract: Embodiments described herein provide a general purpose graphics processing device, comprising a general purpose graphics processing compute block to process a workload including graphics or compute operations, a memory, and a constant folding unit comprising a processing unit to receive a first input shader and metadata for the first input shader, receive a first constant buffer comprising runtime constants for the first input shader, and generate an improved shader from the first input shader and the runtime constants. Other embodiments may be described and claimed.

公开(公告)号：US20200074726A1

公开(公告)日：2020-03-05

申请号：US16115337

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： JOHN GIERACH ,  DANIEL WALSH ,  JOHN FEIT ,  DEVAN BURKE

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06F17/16

Abstract: Apparatus and method for a multi-frequency vertex shader. For example, one embodiment of a graphics processing apparatus comprises a plurality of vertex caches to store vertex data associated with graphics primitives; and graphics execution circuitry to execute vertex shaders operable at different processing rates for different sets of the vertex data, each of the different sets of vertex data to having a different type of identifier associated therewith to identify the vertex data.