公开(公告)号：US20230333855A1

公开(公告)日：2023-10-19

申请号：US18199771

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Nitin N. Garegrat ,  Tony L. Werner ,  Jeff DelChiaro ,  Michael Rotzin ,  Robert T. Rhoades ,  Ujwal Basavaraj Sajjanar ,  Anne Q. Ye

IPC: G06F9/345 ,  G06F9/30

CPC classification number: G06F9/3455 ,  G06F9/30032 ,  G06F9/30036

Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.

公开(公告)号：US20250123843A1

公开(公告)日：2025-04-17

申请号：US18990080

申请日：2024-12-20

Applicant: Intel Corporation

Inventor： Nitin N. Garegrat ,  Tony L. Werner ,  Jeff DelChiaro ,  Michael Rotzin ,  Robert T. Rhoades ,  Ujwal Basavaraj Sajjanar ,  Anne Q. Ye

IPC: G06F9/345 ,  G06F9/30 ,  G06F17/16

Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.

公开(公告)号：US12229560B2

公开(公告)日：2025-02-18

申请号：US18199771

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Nitin N. Garegrat ,  Tony L. Werner ,  Jeff DelChiaro ,  Michael Rotzin ,  Robert T. Rhoades ,  Ujwal Basavaraj Sajjanar ,  Anne Q. Ye

IPC: G06F9/30 ,  G06F9/345 ,  G06F17/16

Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.

公开(公告)号：US11687341B2

公开(公告)日：2023-06-27

申请号：US16556223

申请日：2019-08-29

Applicant: Intel Corporation

Inventor： Nitin N. Garegrat ,  Tony L. Werner ,  Jeff DelChiaro ,  Michael Rotzin ,  Robert T. Rhoades ,  Ujwal Basavaraj Sajjanar ,  Anne Q. Ye

IPC: G06F9/30 ,  G06F9/345

CPC classification number: G06F9/3455 ,  G06F9/30032 ,  G06F9/30036

Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.

公开(公告)号：US20190391811A1

公开(公告)日：2019-12-26

申请号：US16556223

申请日：2019-08-29

Applicant: Intel Corporation

Inventor： Nitin N. Garegrat ,  Tony L. Werner ,  Jeff DelChiaro ,  Michael Rotzin ,  Robert T. Rhoades ,  Ujwal Basavaraj Sajjanar ,  Anne Q. Ye

IPC: G06F9/345 ,  G06F9/30

Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.