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公开(公告)号：US20250123843A1
公开(公告)日：2025-04-17
申请号：US18990080
申请日：2024-12-20
Applicant: Intel Corporation
Inventor： Nitin N. Garegrat , Tony L. Werner , Jeff DelChiaro , Michael Rotzin , Robert T. Rhoades , Ujwal Basavaraj Sajjanar , Anne Q. Ye
Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.
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公开(公告)号：US11204766B2
公开(公告)日：2021-12-21
申请号：US16557187
申请日：2019-08-30
Applicant: Intel Corporation
Inventor： Jason Seung-Min Kim , Nitin N. Garegrat , Anitha Loke , Nasima Parveen , David Y. Fang , Kursad Kiziloglu , Dmitry Sergeyevich Lukiyanchenko , Fabrice Paillet , Andrew Yang
IPC: G06F9/30
Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.
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公开(公告)号：US11520562B2
公开(公告)日：2022-12-06
申请号：US16557959
申请日：2019-08-30
Applicant: Intel Corporation
Inventor： Brian J. Hickmann , Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin
Abstract: A method comprising storing a plurality of entries, each entry of the plurality of entries associated with a portion of a range of input values, each entry of the plurality of entries comprising a set of coefficients defining a power series approximation; selecting first entry of the plurality of entries based on a determination that a floating point input value is within a portion of the range of input values that is associated with the first entry; and calculating an output value by evaluating the power series approximation defined by the set of coefficients of the first entry at the floating point input value.
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公开(公告)号：US20190384575A1
公开(公告)日：2019-12-19
申请号：US16557959
申请日：2019-08-30
Applicant: Intel Corporation
Inventor： Brian J. Hickmann , Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin
Abstract: A method comprising storing a plurality of entries, each entry of the plurality of entries associated with a portion of a range of input values, each entry of the plurality of entries comprising a set of coefficients defining a power series approximation; selecting first entry of the plurality of entries based on a determination that a floating point input value is within a portion of the range of input values that is associated with the first entry; and calculating an output value by evaluating the power series approximation defined by the set of coefficients of the first entry at the floating point input value.
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公开(公告)号：US12229560B2
公开(公告)日：2025-02-18
申请号：US18199771
申请日：2023-05-19
Applicant: Intel Corporation
Inventor： Nitin N. Garegrat , Tony L. Werner , Jeff DelChiaro , Michael Rotzin , Robert T. Rhoades , Ujwal Basavaraj Sajjanar , Anne Q. Ye
Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.
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Patent Agency Ranking
公开(公告)号：US11687341B2
公开(公告)日：2023-06-27
申请号：US16556223
申请日：2019-08-29
Applicant: Intel Corporation
Inventor： Nitin N. Garegrat , Tony L. Werner , Jeff DelChiaro , Michael Rotzin , Robert T. Rhoades , Ujwal Basavaraj Sajjanar , Anne Q. Ye
CPC classification number: G06F9/3455 , G06F9/30032 , G06F9/30036
Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.
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公开(公告)号：US20190391811A1
公开(公告)日：2019-12-26
申请号：US16556223
申请日：2019-08-29
Applicant: Intel Corporation
Inventor： Nitin N. Garegrat , Tony L. Werner , Jeff DelChiaro , Michael Rotzin , Robert T. Rhoades , Ujwal Basavaraj Sajjanar , Anne Q. Ye
Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.
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公开(公告)号：US20230333855A1
公开(公告)日：2023-10-19
申请号：US18199771
申请日：2023-05-19
Applicant: Intel Corporation
Inventor： Nitin N. Garegrat , Tony L. Werner , Jeff DelChiaro , Michael Rotzin , Robert T. Rhoades , Ujwal Basavaraj Sajjanar , Anne Q. Ye
CPC classification number: G06F9/3455 , G06F9/30032 , G06F9/30036
Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.
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公开(公告)号：US11567555B2
公开(公告)日：2023-01-31
申请号：US16557657
申请日：2019-08-30
Applicant: Intel Corporation
Inventor： Jason Seung-Min Kim , Sundar Ramani , Yogesh Bansal , Nitin N. Garegrat , Olivia K. Wu , Mayank Kaushik , Mrinal Iyer , Tom Schebye , Andrew Yang
Abstract: Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.
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公开(公告)号：US11169776B2
公开(公告)日：2021-11-09
申请号：US16457318
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin , Brian J. Hickmann , Valentina Popescu
Abstract: Systems, apparatuses and methods may provide for technology that in response to an identification that one or more hardware units are to execute on a first type of data format, decomposes a first original floating point number to a plurality of first segmented floating point numbers that are to be equivalent to the first original floating point number. The technology may further in response to the identification, decompose a second original floating point number to a plurality of second segmented floating point numbers that are to be equivalent to the second original floating point number. The technology may further execute a multiplication operation on the first and second segmented floating point numbers to multiply the first segmented floating point numbers with the second segmented floating point numbers.
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