公开(公告)号：US09170955B2

公开(公告)日：2015-10-27

申请号：US13685991

申请日：2012-11-27

Applicant: Intel Corporation

Inventor： Andrew T. Forsyth ,  Ramacharan Sundararaman ,  Eric Sprangle ,  John C. Mejia ,  Douglas M. Carmean ,  Edward T. Grochowski ,  Robert D. Cavin

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/126 ,  G06F12/123 ,  Y02D10/13

Abstract: In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括解码逻辑，用于接收和解码第一存储器访问指令以将数据存储在具有第一级的替换状态指示符的高速缓冲存储器中，并将解码的第一存储器访问指令发送到控制逻辑。 反过来，控制逻辑是以第一组高速缓冲存储器的第一种方式存储数据，并且响应于解码的第一存储器访问指令将第一级的替换状态指示符存储在第一方式的元数据字段中 。 描述和要求保护其他实施例。