公开(公告)号：US11487541B2

公开(公告)日：2022-11-01

申请号：US17107134

申请日：2020-11-30

申请人： Intel Corporation

发明人： Jesus Corbal ,  Robert Valentine ,  Roman S. Dubtsov ,  Nikita A. Shustrov ,  Mark J. Charney ,  Dennis R. Bradford ,  Milind B. Girkar ,  Edward T. Grochowski ,  Thomas D. Fletcher ,  Warren E. Ferguson

IPC分类号： G06F9/30 ,  G06F7/544 ,  G06F7/483 ,  G06F9/38

摘要： Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand. Execution circuitry executes the decoded single instruction to perform iterations of packed fused multiply accumulate operations by multiplying packed data elements of the sources of the first type by sub-elements of the scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.

公开(公告)号：US10423411B2

公开(公告)日：2019-09-24

申请号：US14866921

申请日：2015-09-26

申请人： Intel Corporation

发明人： Asit K. Mishra ,  Edward T. Grochowski ,  Jonathan D. Pearce ,  Deborah T. Marr ,  Ehud Cohen ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal San Adrian ,  Robert Valentine ,  Mark J. Charney ,  Christopher J. Hughes ,  Milind B. Girkar

IPC分类号： G06F9/30

摘要： A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

公开(公告)号：US10275243B2

公开(公告)日：2019-04-30

申请号：US15201442

申请日：2016-07-02

申请人： Intel Corporation

发明人： Edward T. Grochowski ,  Asit K. Mishra ,  Robert Valentine ,  Mark J. Charney ,  Simon C. Steely, Jr.

IPC分类号： G06F9/30 ,  G06F9/38

摘要： A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

公开(公告)号：US20190012266A1

公开(公告)日：2019-01-10

申请号：US16115067

申请日：2018-08-28

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F12/1027 ,  G06F12/1009

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US10146535B2

公开(公告)日：2018-12-04

申请号：US15299420

申请日：2016-10-20

申请人： Intel Corporation

发明人： Jesus Corbal ,  Robert Valentine ,  Roman S. Dubtsov ,  Nikita A. Shustrov ,  Mark J. Charney ,  Dennis R. Bradford ,  Milind B. Girkar ,  Edward T. Grochowski ,  Thomas D. Fletcher ,  Warren E. Ferguson

IPC分类号： G06F9/30 ,  G06F7/544

摘要： Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand. Execution circuitry executes the decoded single instruction to perform iterations of packed fused multiply accumulate operations by multiplying packed data elements of the sources of the first type by sub-elements of the scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.

公开(公告)号：US20180173437A1

公开(公告)日：2018-06-21

申请号：US15384178

申请日：2016-12-19

申请人： Intel Corporation

发明人： Asit K. Mishra ,  Deborah T. Marr ,  Edward T. Grochowski

IPC分类号： G06F3/06

CPC分类号： G06F3/0614 ,  G06F3/0646 ,  G06F3/0683 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3877 ,  G06F2212/1016

摘要： First elements of a dense vector to be multiplied with first elements of a first row of a sparse array may be determined. The determined first elements of the dense vector may be written into a memory. A dot product for the first elements of the sparse array and the first elements of the dense vector may be calculated in a plurality of increments by multiplying a subset of the first elements of the sparse array and a corresponding subset of the first elements of the dense vector. A sequence number may be updated after each increment is completed to identify a column number and/or a row number of the sparse array for which the dot product calculations have been completed.

公开(公告)号：US20180165199A1

公开(公告)日：2018-06-14

申请号：US15376647

申请日：2016-12-12

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F12/1027 ,  G06F12/1009

CPC分类号： G06F12/0831 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/621 ,  G06F2212/68

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US20170031729A1

公开(公告)日：2017-02-02

申请号：US15290375

申请日：2016-10-11

申请人： Intel Corporation

发明人： Edward T. Grochowski ,  Michael D. Upton ,  George Z. Chrysos ,  Chunhui Zhang ,  Mohammed L. Al-Aqrabawi

IPC分类号： G06F9/52

CPC分类号： G06F9/52 ,  G06F2209/5014

摘要： Disclosed herein is a generational thread scheduler. One embodiment may be used with processor multithreading logic to execute threads of executable instructions, and a shared resource to be allocated fairly among the threads of executable instructions contending for access to the shared resource. Generational thread scheduling logic may allocate the shared resource efficiently and fairly by granting a first requesting thread access to the shared resource allocating a reservation for the shared resource to each other requesting thread of the executing threads and then blocking the first thread from re-requesting the shared resource until every other thread that has been allocated a reservation, has been granted access to the shared resource. Generation tracking state may be cleared when each requesting thread of the generation that was allocated a reservation has had their request satisfied.

摘要翻译： 这里公开的是一代代线程调度器。 一个实施例可以与处理器多线程逻辑一起使用以执行可执行指令的线程，以及在竞争访问共享资源的可执行指令的线程之间公平分配的共享资源。 生成线程调度逻辑可以通过向共享资源授予对共享资源的预留的第一请求线程访问来对其执行线程的请求线程，然后阻止第一线程重新请求 共享资源，直到已分配了预留的每个其他线程已被授予对共享资源的访问权限。 当分配了预约的生成的每个请求线程已经满足了请求时，可以清除生成跟踪状态。

公开(公告)号：US20170010895A1

公开(公告)日：2017-01-12

申请号：US15276290

申请日：2016-09-26

申请人： Intel Corporation

发明人： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggarwal ,  Prashant Sethi ,  Baiju V. Patel ,  James P. Held

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/48

CPC分类号： G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

摘要翻译： 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。

公开(公告)号：US20160328233A1

公开(公告)日：2016-11-10

申请号：US14704633

申请日：2015-05-05

申请人： INTEL CORPORATION

发明人： Edwin Jan Van Dalen ,  Martinus C. Wezelenburg ,  Steven Roos ,  Edward T. Grochowski ,  Moshe Maor

IPC分类号： G06F9/30 ,  H03H17/02

CPC分类号： G06F9/30036 ,  G06F9/3001 ,  G06F9/3893 ,  G06F9/455 ,  H03H17/0202 ,  H03H17/06 ,  H03H2017/0298

摘要： A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.

摘要翻译： 处理器包括解码单元，用于解码指示一个或多个源打包数据操作数，多个FIR滤波器系数和目的地存储位置的压缩有限脉冲响应（FIR）滤波器指令。 源操作数包括第一数量的数据元素和第二数量的附加数据元素。 第二个数字是少于FIR滤波器抽头的数量。 响应于被解码的打包FIR滤波器指令，执行单元是存储结果打包数据操作数。 结果打包数据操作数包括第一数量的FIR滤波数据元素，每个FIR滤波数据元素将基于多个FIR滤波器系数的乘积和来自一个或多个源打包数据操作数的不同对应的数据元素的组合， 其数量与FIR滤波器抽头的数量相等。