公开(公告)号：US10860319B2

公开(公告)日：2020-12-08

申请号：US15941976

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Mark Dechene ,  Manjunath Shevgoor ,  Faruk Guvenilir ,  Zhongying Zhang ,  Jonathan Perry

IPC: G06F9/30 ,  G06F9/32 ,  G06F12/1027 ,  G06F9/38

Abstract: An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.