公开(公告)号：US20230409481A1

公开(公告)日：2023-12-21

申请号：US18320780

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Stanislav Shwartsman ,  Anant Nori ,  Shankar Balachandran ,  Elad Shtiegmann ,  Vineeth Mekkat ,  Manjunath Shevgoor ,  Sourabh Alurkar

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

公开(公告)号：US10761844B2

公开(公告)日：2020-09-01

申请号：US16023407

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Manjunath Shevgoor ,  Mark J. Dechene ,  Stanislav Shwartsman ,  Pavel I. Kryukov

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/1027

Abstract: Disclosed embodiments relate to predicting load data. In one example, a processor a pipeline having stages ordered as fetch, decode, allocate, write back, and commit, a training table to store an address, predicted data, a state, and a count of instances of unchanged return data, and tracking circuitry to determine, during one or more of the allocate and decode stages, whether a training table entry has a first state and matches a fetched first load instruction, and, if so, using the data predicted by the entry during the execute stage, the tracking circuitry further to update the training table during or after the write back stage to set the state of the first load instruction in the training table to the first state when the count reaches a first threshold.

公开(公告)号：US11693780B2

公开(公告)日：2023-07-04

申请号：US17391962

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Stanislav Shwartsman ,  Anant Nori ,  Shankar Balachandran ,  Elad Shtiegmann ,  Vineeth Mekkat ,  Manjunath Shevgoor ,  Sourabh Alurkar

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

公开(公告)号：US10915320B2

公开(公告)日：2021-02-09

申请号：US16231305

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Xi Chen ,  Manjunath Shevgoor

IPC: G06F9/302 ,  G06F9/315 ,  G06F9/30 ,  G06F9/54 ,  G06F9/38

Abstract: A processor includes an instruction fetch circuit to retrieve instructions from memory, and a decode unit circuit to decode retrieved instructions. The decode unit circuit identifies a shift instruction, accumulates a shift folded immediate value to track a number of bit positions shifted for a source register, and prevents the shift instruction from allocation to an execution unit of the processor.

公开(公告)号：US20190095203A1

公开(公告)日：2019-03-28

申请号：US15719290

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Sofia Pediaditaki ,  Ethan Schuchman ,  Rangeen Basu Roy Chowdhury ,  Manjunath Shevgoor

IPC: G06F9/30 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/0811 ,  G06F9/52

CPC classification number: G06F9/3004 ,  G06F9/30036 ,  G06F9/524 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0848 ,  G06F12/0875 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/282 ,  G06F2212/283 ,  G06F2212/6042 ,  G06F2212/621

Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.

公开(公告)号：US20240111679A1

公开(公告)日：2024-04-04

申请号：US17958334

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Seth Pugsley ,  Mark Dechene ,  Ryan Carlson ,  Manjunath Shevgoor

IPC: G06F12/0862 ,  G06F9/345 ,  G06F12/0882

CPC classification number: G06F12/0862 ,  G06F9/3455 ,  G06F12/0882

Abstract: Techniques for prefetching by a hardware processor are described. In certain examples, a hardware processor includes execution circuitry, cache memories, and prefetcher circuitry. The execution circuitry is to execute instructions to access data at a memory address. The cache memories include a first cache memory at a first cache level and a second cache memory at a second cache level. The prefetcher circuitry is to prefetch the data from a system memory to at least one of the plurality of cache memories, and it includes a first-level prefetcher to prefetch the data to the first cache memory, a second-level prefetcher to prefetch the data to the second cache memory, and a plurality of prefetch filters. One of the prefetch filters is to filter exclusively for the first-level prefetcher. Another of the prefetch filters is to maintain a history of demand and prefetch accesses to pages in the system memory and to use the history to provide training information to the second-level prefetcher.

公开(公告)号：US20200210339A1

公开(公告)日：2020-07-02

申请号：US16234135

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Stanislav Shwartsman ,  Anant Nori ,  Shankar Balachandran ,  Elad Shtiegmann ,  Vineeth Mekkat ,  Manjunath Shevgoor ,  Sourabh Alurkar

IPC: G06F12/0862

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

公开(公告)号：US20190087341A1

公开(公告)日：2019-03-21

申请号：US15709285

申请日：2017-09-19

Applicant: INTEL CORPORATION

Inventor： Seth H. Pugsley ,  Manjunath Shevgoor ,  Christopher B. Wilkerson

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/283 ,  G06F2212/602 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to generate prefetch requests to prefetch data into the mid-level cache; and a prefetcher selector to select a prefetcher configuration for the first prefetcher and the second prefetcher based on at least one memory access metric, wherein the prefetcher configuration is to specify whether the first prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of a particular page and whether the second prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of the particular page.

公开(公告)号：US12216581B2

公开(公告)日：2025-02-04

申请号：US18320780

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Stanislav Shwartsman ,  Anant Nori ,  Shankar Balachandran ,  Elad Shtiegmann ,  Vineeth Mekkat ,  Manjunath Shevgoor ,  Sourabh Alurkar

IPC: G06F12/0862

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

公开(公告)号：US20210365377A1

公开(公告)日：2021-11-25

申请号：US17391962

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Stanislav Shwartsman ,  Anant Nori ,  Shankar Balachandran ,  Elad Shtiegmann ,  Vineeth Mekkat ,  Manjunath Shevgoor ,  Sourabh Alurkar

IPC: G06F12/0862

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.