公开(公告)号：US20190181249A1

公开(公告)日：2019-06-13

申请号：US16306540

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： SASIKANTH MANIPATRUNI ,  ANURAG CHAUDHRY ,  DMITRI E. NIKONOV ,  JASMEET S. CHAWLA ,  CHRISTOPHER J. WIEGAND ,  KANWALJIT SINGH ,  UYGAR E. AVCI ,  IAN A. YOUNG

IPC: H01L29/66 ,  H01L29/47 ,  H01L29/78 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/06 ,  H01L21/285

Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.