公开(公告)号：US20190355826A1

公开(公告)日：2019-11-21

申请号：US16474874

申请日：2017-04-11

Applicant: INTEL CORPORATION

Inventor： UYGAR E. AVCI ,  DANIEL H. MORRIS ,  IAN A. YOUNG

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including a channel region, a gate dielectric between the gate electrode and the channel region, a first layer between the gate dielectric and the gate electrode, the first layer comprising temperature compensation material. In addition, the integrate circuit includes a source region adjacent to the channel region, a source metal contact on the source region, a drain region adjacent to the channel region, and a drain metal contact on the drain region. The temperature compensation material has a temperature dependent band structure, work-function, or polarization that dynamically adjusts the threshold voltage of the transistor in response to increased operating temperature to maintain the off-state current Ioff stable or otherwise within an acceptable tolerance. The temperature compensation material may be used in conjunction with a work function material to help provide desired performance at lower or non-elevated temperatures.

公开(公告)号：US20190181249A1

公开(公告)日：2019-06-13

申请号：US16306540

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： SASIKANTH MANIPATRUNI ,  ANURAG CHAUDHRY ,  DMITRI E. NIKONOV ,  JASMEET S. CHAWLA ,  CHRISTOPHER J. WIEGAND ,  KANWALJIT SINGH ,  UYGAR E. AVCI ,  IAN A. YOUNG

IPC: H01L29/66 ,  H01L29/47 ,  H01L29/78 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/06 ,  H01L21/285

Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.