公开(公告)号：US20210041934A1

公开(公告)日：2021-02-11

申请号：US17080395

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： KINCHIT DESAI ,  SANJEEV JAHAGIRDAR ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY

IPC: G06F1/3237 ,  G06N3/04 ,  G06N3/08 ,  G06F1/3234 ,  G06F1/3206

Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.

公开(公告)号：US20190041961A1

公开(公告)日：2019-02-07

申请号：US16144538

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： KINCHIT DESAI ,  SANJEEV JAHAGIRDAR ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY

IPC: G06F1/32 ,  G06N3/08 ,  G06N3/04

Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.