公开(公告)号：US20180286009A1

公开(公告)日：2018-10-04

申请号：US15992642

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： JEFFERY S. BOLES ,  HEMA C. NALLURI ,  BALAJI VEMBU ,  MICHAEL APODACA ,  ALTUG KOKER ,  LALIT K. SAPTARSHI

IPC: G06T1/20 ,  G06F3/06 ,  G06F12/0846 ,  G06T1/60 ,  G09G5/36

Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.

公开(公告)号：US20180012328A1

公开(公告)日：2018-01-11

申请号：US15204402

申请日：2016-07-07

Applicant: Intel Corporation

Inventor： Jeffery S. Boles ,  HEMA C. NALLURI ,  BALAJI VEMBU ,  PRITAV H. SHAH ,  MICHAEL APODACA ,  MURALI RAMADOSS ,  LALIT K. SAPTARSHI

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20

Abstract: A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.