公开(公告)号：US20210349848A1

公开(公告)日：2021-11-11

申请号：US17321885

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ARAVINDH ANANTARAMAN ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  ELMOUSTAPHA OULD-AHMED-VALL ,  VALENTIN ANDREI ,  SUBRAMANIAM MAIYURAN ,  NICOLAS GALOPPO VON BORRIES ,  VARGHESE GEORGE ,  MIKE MACPHERSON ,  BEN ASHBAUGH ,  MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  WILLIAM SADLER ,  JONATHAN PEARCE ,  SUNGYE KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180293183A1

公开(公告)日：2018-10-11

申请号：US15482690

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/1027 ,  G06F12/0802

CPC classification number: G06F13/16 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F13/4068 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/60 ,  G06F2212/68

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20210056051A1

公开(公告)日：2021-02-25

申请号：US17008991

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

IPC: G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20200210246A1

公开(公告)日：2020-07-02

申请号：US16696848

申请日：2019-11-26

Applicant: Intel Corporation

Inventor： PRASOONKUMAR SURTI ,  DAVID COWPERTHWAITE ,  ABHISHEK R. APPU ,  JOYDEEP RAY ,  VASANTH RANGANATHAN ,  ALTUG KOKER ,  BALAJI VEMBU

IPC: G06F9/50

Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.

公开(公告)号：US20180308195A1

公开(公告)日：2018-10-25

申请号：US15493233

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： BALAJI VEMBU ,  ALTUG KOKER ,  JOYDEEP RAY

IPC: G06T1/20 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T2200/04

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising multiple processing units and a pipeline manager to distribute a thread group to the multiple processing units, wherein the pipeline manager is to distribute the thread group as multiple thread sub-groups.

公开(公告)号：US20180293776A1

公开(公告)日：2018-10-11

申请号：US15482677

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  BALAJI VEMBU ,  ALTUG KOKER ,  NIRANJAN L. COORAY ,  JOSH B. MASTRONARDE

IPC: G06T15/00 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50

Abstract: An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

公开(公告)号：US20180286009A1

公开(公告)日：2018-10-04

申请号：US15992642

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： JEFFERY S. BOLES ,  HEMA C. NALLURI ,  BALAJI VEMBU ,  MICHAEL APODACA ,  ALTUG KOKER ,  LALIT K. SAPTARSHI

IPC: G06T1/20 ,  G06F3/06 ,  G06F12/0846 ,  G06T1/60 ,  G09G5/36

Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.

公开(公告)号：US20200210472A1

公开(公告)日：2020-07-02

申请号：US16696854

申请日：2019-11-26

Applicant: Intel Corporation

Inventor： BARNAN DAS ,  MAYURESH M. VARERKAR ,  NARAYAN BISWAL ,  STANLEY J. BARAN ,  GOKCEN CILINGIR ,  NILESH V. SHAH ,  ARCHIE SHARMA ,  SHERINE ABDELHAK ,  PRANEETHA KOTHA ,  NEELAY PANDIT ,  JOHN C. WEAST ,  MIKE B. MACPHERSON ,  DUKHWAN KIM ,  LINDA L. HURD ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY

IPC: G06F16/583 ,  G06F16/783 ,  G06K9/00 ,  G06K9/62

Abstract: A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.

公开(公告)号：US20200167221A1

公开(公告)日：2020-05-28

申请号：US16203578

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： BALAJI VEMBU ,  BRYAN WHITE ,  ANKUR SHAH ,  MURALI RAMADOSS ,  DAVE PUFFER ,  ALTUG KOKER ,  ADITYA NAVALE ,  MAHESH NATU

IPC: G06F11/07 ,  G06T15/00

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

公开(公告)号：US20200005516A1

公开(公告)日：2020-01-02

申请号：US16024821

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： MICHAEL APODACA ,  ANKUR SHAH ,  BEN ASHBAUGH ,  BRANDON FLIFLET ,  HEMA NALLURI ,  PATTABHIRAMAN K ,  PETER DOYLE ,  JOSEPH KOSTON ,  JAMES VALERIO ,  MURALI RAMADOSS ,  ALTUG KOKER ,  ADITYA NAVALE ,  PRASOONKUMAR SURTI ,  BALAJI VEMBU

IPC: G06T15/00

Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.