公开(公告)号：US20170357831A1

公开(公告)日：2017-12-14

申请号：US15495644

申请日：2017-04-24

Applicant: INTEL CORPORATION

Inventor： HEMA C. NALLURI ,  ADITYA NAVALE ,  MURALI RAMADOSS

IPC: G06F21/74 ,  G06F21/84 ,  G06T15/00

CPC classification number: G06F21/74 ,  G06F21/84 ,  G06T15/005

Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged. A graphics processing unit (GPU) can receive the privilege-designated batch buffers from the KMD, and is configured to disallow execution of any privileged command from a non-privileged batch buffer, while any privileged commands from privileged batch buffers are unrestricted by the GPU

公开(公告)号：US20200167221A1

公开(公告)日：2020-05-28

申请号：US16203578

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： BALAJI VEMBU ,  BRYAN WHITE ,  ANKUR SHAH ,  MURALI RAMADOSS ,  DAVE PUFFER ,  ALTUG KOKER ,  ADITYA NAVALE ,  MAHESH NATU

IPC: G06F11/07 ,  G06T15/00

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

公开(公告)号：US20200005516A1

公开(公告)日：2020-01-02

申请号：US16024821

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： MICHAEL APODACA ,  ANKUR SHAH ,  BEN ASHBAUGH ,  BRANDON FLIFLET ,  HEMA NALLURI ,  PATTABHIRAMAN K ,  PETER DOYLE ,  JOSEPH KOSTON ,  JAMES VALERIO ,  MURALI RAMADOSS ,  ALTUG KOKER ,  ADITYA NAVALE ,  PRASOONKUMAR SURTI ,  BALAJI VEMBU

IPC: G06T15/00

Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.

公开(公告)号：US20190287205A1

公开(公告)日：2019-09-19

申请号：US15922836

申请日：2018-03-15

Applicant: Intel Corporation

Inventor： MURALI RAMADOSS ,  PENNE LEE ,  ANKUR SHAH ,  PING LIU ,  JOSEPH KOSTON

IPC: G06T1/20

Abstract: An apparatus and method for virtualized scheduling. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising a plurality of graphics processing engines, each of the graphics processing engines usable to execute graphics program code for a plurality of graphics contexts, each of the graphics contexts associated with a particular user mode driver (UMD); and a scheduler to schedule the graphics program code for execution on the plurality of graphics engines, the scheduler comprising an integrated context queue to store program code from all of the graphics contexts, the scheduler to select graphics processing engines to execute the program code from each context based on a detected load and/or availability of each graphics processing engine and to determine an order for executing the program code from each context based on relative priorities associated with the different contexts.

公开(公告)号：US20230029176A1

公开(公告)日：2023-01-26

申请号：US17868448

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ARAVINDH ANANTARAMAN ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  ELMOUSTAPHA OULD-AHMED-VALL ,  VALENTIN ANDREI ,  SUBRAMANIAM MAIYURAN ,  NICOLAS GALOPPO VON BORRIES ,  VARGHESE GEORGE ,  MIKE MACPHERSON ,  BEN ASHBAUGH ,  MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  WILLIAM SADLER ,  JONATHAN PEARCE ,  SUNGYE KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200327636A1

公开(公告)日：2020-10-15

申请号：US16790397

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： MURALI RAMADOSS ,  PENNE LEE ,  ANKUR SHAH ,  PING LIU ,  JOSEPH KOSTON

IPC: G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F9/50

Abstract: An apparatus and method for virtualized scheduling. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising a plurality of graphics processing engines, each of the graphics processing engines usable to execute graphics program code for a plurality of graphics contexts, each of the graphics contexts associated with a particular user mode driver (UMD); and a scheduler to schedule the graphics program code for execution on the plurality of graphics engines, the scheduler comprising an integrated context queue to store program code from all of the graphics contexts, the scheduler to select graphics processing engines to execute the program code from each context based on a detected load and/or availability of each graphics processing engine and to determine an order for executing the program code from each context based on relative priorities associated with the different contexts.

公开(公告)号：US20200293456A1

公开(公告)日：2020-09-17

申请号：US16354859

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  NIRAN COORAY ,  WILLIAM B. SADLER ,  JONATHAN D. PEARCE ,  MARIAN ALIN PETRE ,  BEN ASHBAUGH ,  ELMOUSTAPHA OULD-AHMED-VALL ,  NICOLAS GALOPPO VON BORRIES ,  ALTUG KOKER ,  ARAVINDH ANANTARAMAN ,  SUBRAMANIAM MAIYURAN ,  VARGHESE GEORGE ,  SUNGYE KIM ,  ANDREI VALENTIN

IPC: G06F12/1009 ,  G06N20/00

Abstract: Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210349848A1

公开(公告)日：2021-11-11

申请号：US17321885

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ARAVINDH ANANTARAMAN ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  ELMOUSTAPHA OULD-AHMED-VALL ,  VALENTIN ANDREI ,  SUBRAMANIAM MAIYURAN ,  NICOLAS GALOPPO VON BORRIES ,  VARGHESE GEORGE ,  MIKE MACPHERSON ,  BEN ASHBAUGH ,  MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  WILLIAM SADLER ,  JONATHAN PEARCE ,  SUNGYE KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210272349A1

公开(公告)日：2021-09-02

申请号：US17306769

申请日：2021-05-03

Applicant: Intel Corporation

Inventor： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  DANIEL JOHNSTON ,  JASON SURPRISE ,  PRASOONKUMAR SURTI ,  SUBRAMANIAM MAIYURAN ,  PETER DOYLE ,  SAURABH SHARMA ,  ANKUR SHAH ,  MURALI RAMADOSS

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20200293365A1

公开(公告)日：2020-09-17

申请号：US16354919

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： NIRAN COORAY ,  WILLIAM B. SADLER ,  JONATHAN D. PEARCE ,  MARIAN ALIN PETRE ,  BEN ASHBAUGH ,  MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  ANKUR N SHAH ,  RAJESH SANKARAN

IPC: G06F9/48 ,  G06T1/60 ,  G06T1/20 ,  G06F12/1009

Abstract: Methods and apparatus relating to transactional page fault handling. In an example, an apparatus comprises a processor to divide an execution thread of a graphics workload into a set of transactions which are to be executed atomically, initiate the execution of the thread, and manage the execution of the thread according to one of a first protocol in response to a determination that a page fault occurred in the execution of a transaction, or a second protocol in response to a determination that a page fault did not occur in the execution of a transaction. Other embodiments are also disclosed and claimed.