公开(公告)号：US20240413550A1

公开(公告)日：2024-12-12

申请号：US18805632

申请日：2024-08-15

Applicant: Intel Corporation

Inventor： Chenghai Yan ,  Wenzhi Wang ,  Qihang Shang ,  Tao Xu ,  Weijiao Jiang ,  Xinjun Zhang ,  Lei Wang ,  Xiaorui Xu

IPC: H01R12/70 ,  H01R13/6461

Abstract: An apparatus and method for reducing differential cross-talk in a CPU pin arrangement of a server motherboard are described. The CPU pin arrangement has pin patterns that are arranged in a square, separated from each other, and are mirrored around an axis between the pin patterns. Each pin pattern has pins that each include a main body with a lateral asymmetric cross-section, a first connector extending from one end of the main body and coupled to the motherboard through solder, and a second connector extending from an opposing end of the main body and coupled to the CPU through a pressure contact.

公开(公告)号：US20240274521A1

公开(公告)日：2024-08-15

申请号：US18570455

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Chenghai Yan ,  Lei Wang ,  Maoxin Yin ,  Wenzhi Wang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/66

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/14 ,  H01L24/16 ,  H01L2223/6661 ,  H01L2224/1403 ,  H01L2224/16227

Abstract: Methods, apparatus, systems, and articles of manufacture to reduce impedance discontinuities and crosstalk in integrated circuit packages are disclosed. A disclosed apparatus includes: a package substrate, and a ball grid array on a first surface of the package substrate. The ball grid array includes a first ball and a second ball adjacent the first ball. The ball grid array is to enable the package substrate to be electrically coupled to a circuit board. The apparatus further includes a metal interconnect within the package substrate. The metal interconnect is electrically coupled to the first ball. The metal interconnect includes an inductive loop that extends toward the second ball.