公开(公告)号：US20200243376A1

公开(公告)日：2020-07-30

申请号：US16260632

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Chieh-Jen KU ,  Bernhard SELL ,  Pei-Hua WANG ,  Harish GANAPATHY ,  Leonard C. PIPES

IPC: H01L21/762 ,  H01L27/108

Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.

公开(公告)号：US20220310601A1

公开(公告)日：2022-09-29

申请号：US17211745

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Cory WEBER ,  Stephen M. CEA ,  Leonard C. PIPES ,  Seahee HWANGBO ,  Rishabh MEHANDRU ,  Patrick KEYS ,  Jack YAUNG ,  Tzu-Min OU

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm3. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.