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    Timestamp alignment for multiple nodes
    1.
    发明授权
    Timestamp alignment for multiple nodes 有权

    公开(公告)号：US12160495B2

    公开(公告)日：2024-12-03

    申请号：US17475200

    申请日：2021-09-14

    Applicant: Intel Corporation

    Inventor： Mark Bordogna ,  Jonathan A. Robinson ,  Srinivasan S. Iyengar

    IPC: H04L7/00

    Abstract: Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.

    One-step time stamping of synchronization packets for networked devices
    2.
    发明授权
    One-step time stamping of synchronization packets for networked devices 有权

    公开(公告)号：US10931391B2

    公开(公告)日：2021-02-23

    申请号：US15717649

    申请日：2017-09-27

    Applicant: Intel Corporation

    Inventor： Sita Rama Chandrasekhar Mallela ,  Mark Bordogna

    IPC: H04J3/06 ,  H04L29/06

    Abstract: Electronic devices coupled to a network may exchange messages containing time-of-day information synchronization of the internal clocks. The information exchanged may include the instant at which a message leaves the electronic device. Discussed herein are methods and systems that allow 1-step timestamping of messages containing time-of-day information. The 1-step timestamping methods and systems may reduce the impact of non-deterministic time delays in the transmit path (e.g., encryption, expansion, inclusion of tags), and may improve the accuracy of the time-of-day information of the packets. For example, systems and methods may allow accurate 1-step timestamping of IEEE 1588 Precision Time Protocol packets with the uncertainty of delays from MACSec encryption or other security mechanisms. Some embodiments employ estimation non-deterministic delay of previously transmitted packets to estimate the state of the transmit path. Some embodiments include communication channels to allow circuitry in transmit path to report the state.

    Method and apparatus for data plane control of network time sync protocol in multi-host systems
    3.
    发明授权
    Method and apparatus for data plane control of network time sync protocol in multi-host systems 有权

    公开(公告)号：US12177003B2

    公开(公告)日：2024-12-24

    申请号：US17205869

    申请日：2021-03-18

    Applicant: Intel Corporation

    Inventor： Mark Bordogna ,  Srinivasan S. Iyengar

    IPC: H04J3/06 ,  H04L43/106 ,  H04L69/28

    Abstract: Methods and apparatus for data plane control of network time sync protocol in multi-host systems. A network interface controller (NIC) is configured to implement a network data plane that is associated with a software-based control plane implemented in the multi-host system. The NIC includes a primary timer and secondary timers at distributed endpoints such as network ports. The NIC receives network time packets having network timestamps and employs a secondary timer to associate a local timestamp with the packets. The network and local timestamps are compared by a network intellectual property block (network IP) in the data plane datapath to adjust the primary and secondary timer(s) to match the network time. The network IP uses a 2-bit wire protocol to increment and/or decrement the primary and secondary timer(s) that enables the timers to be adjusted with a nanosecond granularity.

    One-Step Time Stamping Of Synchronization Packets For Networked Devices
    4.
    发明申请
    One-Step Time Stamping Of Synchronization Packets For Networked Devices 审中-公开

    公开(公告)号：US20190097745A1

    公开(公告)日：2019-03-28

    申请号：US15717649

    申请日：2017-09-27

    Applicant: Intel Corporation

    Inventor： Sita Rama Chandrasekhar Mallela ,  Mark Bordogna

    IPC: H04J3/06

    Abstract: Electronic devices coupled to a network may exchange messages containing time-of-day information synchronization of the internal clocks. The information exchanged may include the instant at which a message leaves the electronic device. Discussed herein are methods and systems that allow 1-step timestamping of messages containing time-of-day information. The 1-step timestamping methods and systems may reduce the impact of non-deterministic time delays in the transmit path (e.g., encryption, expansion, inclusion of tags), and may improve the accuracy of the time-of-day information of the packets. For example, systems and methods may allow accurate 1-step timestamping of IEEE 1588 Precision Time Protocol packets with the uncertainty of delays from MACSec encryption or other security mechanisms. Some embodiments employ estimation non-deterministic delay of previously transmitted packets to estimate the state of the transmit path. Some embodiments include communication channels to allow circuitry in transmit path to report the state.

    Timestamp alignment across multiple computing nodes
    5.
    发明授权
    Timestamp alignment across multiple computing nodes 有权

    公开(公告)号：US11693448B2

    公开(公告)日：2023-07-04

    申请号：US16726684

    申请日：2019-12-24

    Applicant: Intel Corporation

    Inventor： Mark Bordogna ,  Jonathan A. Robinson

    IPC: G06F1/14 ,  H04L43/106 ,  G06F9/54 ,  G06F1/12

    CPC classification number: G06F1/14 ,  G06F1/12 ,  G06F9/542 ,  H04L43/106

    Abstract: Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.

    High accuracy time stamping for multi-lane ports
    6.
    发明授权
    High accuracy time stamping for multi-lane ports 有权

    公开(公告)号：US11265096B2

    公开(公告)日：2022-03-01

    申请号：US16410275

    申请日：2019-05-13

    Applicant: Intel Corporation

    Inventor： Mark Bordogna ,  Janardhan Satyanarayana ,  Yoni Landau ,  Diwakar Suvvari

    IPC: H04J3/07 ,  H04J3/06 ,  H04L1/00 ,  H04L43/106

    Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.

    Timestamp alignment across multiple computing nodes
    7.
    发明授权
    Timestamp alignment across multiple computing nodes 有权

    公开(公告)号：US12222750B2

    公开(公告)日：2025-02-11

    申请号：US18198150

    申请日：2023-05-16

    Applicant: Intel Corporation

    Inventor： Mark Bordogna ,  Jonathan A. Robinson

    IPC: G06F1/14 ,  G06F1/12 ,  G06F9/54 ,  H04L43/106

    Abstract: Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.

    TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION
    10.
    发明申请
    TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION 有权

    公开(公告)号：US20230016505A1

    公开(公告)日：2023-01-19

    申请号：US17948965

    申请日：2022-09-20

    Applicant: Intel Corporation

    Inventor： Yoni Landau ,  Janardhan Satyanarayana ,  Assaf Benhamou ,  Mark Bordogna

    IPC: H04L43/106 ,  H04L69/22 ,  H04L1/00

    Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.

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