公开(公告)号：US09541983B2

公开(公告)日：2017-01-10

申请号：US14919780

申请日：2015-10-22

Applicant: Intel Corporation

Inventor： Barnes Cooper ,  Jeffrey R Wilcox ,  Michael N Derr ,  Neil W Songer ,  Craig S Forbell

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心和电源管理逻辑。 功率管理逻辑可以是响应于处理器中的降低功率状态期间的第一中断事件而设置基于平台等待时间容限的退出定时器，阻止第一多个中断事件中断降低的功率状态，以及 响应于退出定时器的到期，终止降低的功率状态。 描述和要求保护其他实施例。

公开(公告)号：US09195292B2

公开(公告)日：2015-11-24

申请号：US13927746

申请日：2013-06-26

Applicant: Intel Corporation

Inventor： Barnes Cooper ,  Jeffrey R Wilcox ,  Michael N Derr ,  Neil W Songer ,  Craig S Forbell

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心和电源管理逻辑。 功率管理逻辑可以是响应于处理器中的降低功率状态期间的第一中断事件而设置基于平台等待时间容限的退出定时器，阻止第一多个中断事件中断降低的功率状态，以及 响应于退出定时器的到期，终止降低的功率状态。 描述和要求保护其他实施例。