公开(公告)号：US20210048962A1

公开(公告)日：2021-02-18

申请号：US17084301

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Kapil Karkra ,  Mariusz Barczak ,  Michal Wysoczanski ,  Sanjeev Trika ,  James Guilmart

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage access to a storage system that includes a first persistent storage device and a second persistent storage device, capture input/output telemetry for a workload on the storage system, determine one or more write reduction factors and one or more write invalidation factors for the workload based on the captured input/output telemetry, and allocate storage for the workload between the first persistent storage device and the second persistent storage device based on the one or more write reduction factors and the one or more write invalidation factors. Other embodiments are disclosed and claimed.

公开(公告)号：US10599585B2

公开(公告)日：2020-03-24

申请号：US15466986

申请日：2017-03-23

Applicant: Intel Corporation

Inventor： Michal Wysoczanski ,  Mariusz Barczak

IPC: G06F12/123

Abstract: A method and apparatus for caching data accessed in a storage device, which include a selection of a list from a plurality of lists based on a cache block accessed from a cache memory, the cache memory being partitioned into a plurality of cache portions, each of the plurality of lists being assigned to a respective cache portion of the plurality of cache portions, each of the plurality of lists indicating an order in which cache blocks of the respective cache portion were accessed. Furthermore, a determination as to whether the accessed cache block meets a list update criteria, and an update the order in which cache blocks, assigned to the selected list, were accessed from the cache memory based on determining the accessed cache block meets the list update criteria may be included.

公开(公告)号：US12093563B2

公开(公告)日：2024-09-17

申请号：US17084301

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Kapil Karkra ,  Mariusz Barczak ,  Michal Wysoczanski ,  Sanjeev Trika ,  James Guilmart

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0688 ,  G06F2212/7201

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage access to a storage system that includes a first persistent storage device and a second persistent storage device, capture input/output telemetry for a workload on the storage system, determine one or more write reduction factors and one or more write invalidation factors for the workload based on the captured input/output telemetry, and allocate storage for the workload between the first persistent storage device and the second persistent storage device based on the one or more write reduction factors and the one or more write invalidation factors. Other embodiments are disclosed and claimed.

公开(公告)号：US20180276139A1

公开(公告)日：2018-09-27

申请号：US15466986

申请日：2017-03-23

Applicant: Intel Corporation

Inventor： Michal Wysoczanski ,  Mariusz Barczak

IPC: G06F12/122 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/0808

Abstract: A method and apparatus for caching data accessed in a storage device, which include a selection of a list from a plurality of lists based on a cache block accessed from a cache memory, the cache memory being partitioned into a plurality of cache portions, each of the plurality of lists being assigned to a respective cache portion of the plurality of cache portions, each of the plurality of lists indicating an order in which cache blocks of the respective cache portion were accessed. Furthermore, a determination as to whether the accessed cache block meets a list update criteria, and an update the order in which cache blocks, assigned to the selected list, were accessed from the cache memory based on determining the accessed cache block meets the list update criteria may be included.