公开(公告)号：US09921914B2

公开(公告)日：2018-03-20

申请号：US14931730

申请日：2015-11-03

Applicant: Intel Corporation

Inventor： Slawomir Ptak ,  Sanjeev N Trika ,  Piotr Wysocki ,  Kapil Karkra ,  Rajib Ghosal

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1096 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0689

Abstract: An apparatus includes a plurality of drives configured as a redundant array of independent disks (RAID) and drive array controller logic to: calculate a first partial parity log (PPL) value for a first write operation that targets a first active stripe of the plurality of drives; store the first PPL value in a first pre-allocated portion of the plurality of drives that depends on a first number associated with the first active stripe; calculate a second PPL value for a second write operation that targets a second active stripe of the plurality of drives; and store the second PPL value in a second pre-allocated portion of the plurality of drives that depends on a second number associated with the second active stripe.

公开(公告)号：US20230136091A1

公开(公告)日：2023-05-04

申请号：US18148478

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Kapil Karkra ,  Filip Schmole ,  Pankaj Kumar

IPC: G06F9/46

Abstract: Technology described herein provides an improved system architecture for offloading infrastructure tasks using a multi-root switch with logic to route, via a switch, application data in a data transfer message between a physical storage device and a host system, the host system interfacing with a virtual function of an IPU, by remapping a transaction identifier field in the data transfer message between a first transaction identifier associated with the virtual function and a second transaction identifier associated with the physical storage device, where the physical storage device is managed by the IPU, and where to route the application data between the host system and the physical storage device includes to bypass temporary storage of the application data in a memory local to the IPU. In some examples a remapping table holds the first transaction identifier and the second transaction identifier.

公开(公告)号：US10481979B2

公开(公告)日：2019-11-19

申请号：US15718031

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Marcin Pioch ,  Kapil Karkra ,  Piotr Wysocki ,  Slawomir Ptak

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/00

Abstract: According to various aspects, a storage system is provided, the storage system including a multiplicity of storage devices, and one or more processors configured to store user data on the multiplicity of storage devices, the stored user data being distributed among the multiplicity of storage devices together with redundancy data and with log data; generate a classification associated with the redundancy data and the log data to provide classified redundancy data and classified log data, and write the classified redundancy data and the classified log data on the respective storage device of the multiplicity of storage devices according to the classification associated therewith.

公开(公告)号：US20230051328A1

公开(公告)日：2023-02-16

申请号：US17819435

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： Mariusz Barczak ,  Wojciech Malikowski ,  Mateusz Kozlowski ,  Lukasz Lasek ,  Artur Paszkiewicz ,  Kapil Karkra

IPC: G06F12/10

Abstract: Systems, apparatuses, and methods provide for a memory controller to manage a tiered memory including a zoned namespace drive memory capacity tier. For example, a memory controller includes logic to translate a standard zoned namespace drive address associated with a user write to a tiered memory address write. The tiered memory address write is associated with the tiered memory including the persistent memory cache tier and the zoned namespace drive memory capacity tier. A plurality of tiered memory address writes are collected, where the plurality of tiered memory address writes include the tiered memory address write and other tiered memory address writes in the persistent memory cache tier. The collected plurality of tiered memory address writes are transferred from the persistent memory cache tier to the zoned namespace drive memory capacity tier, via an append-type zoned namespace drive write command.

公开(公告)号：US11068175B2

公开(公告)日：2021-07-20

申请号：US16229679

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Marcin Pioch ,  Michael Mesnier ,  Anand Ramalingam ,  Benjamin Boyer ,  Kapil Karkra ,  Piotr Wysocki

IPC: G06F3/06 ,  G06F12/1009

Abstract: A system including a storage drive and a semiconductor apparatus coupled to the storage drive, is provided. The semiconductor apparatus may include one or more substrates and logic coupled to the one or more substrates, the logic coupled to the one or more substrates to: initiate managing resources of the storage drive and, if the storage drive loses capacity, determine an amount of capacity loss, create a reserved file that is associated with logical memory space in a file system, based on the amount of the capacity loss, and erase at least a portion of the reserved file so that logical memory space associated with an un-erased portion of the reserved file is usable by the storage drive.

公开(公告)号：US20210048962A1

公开(公告)日：2021-02-18

申请号：US17084301

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Kapil Karkra ,  Mariusz Barczak ,  Michal Wysoczanski ,  Sanjeev Trika ,  James Guilmart

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage access to a storage system that includes a first persistent storage device and a second persistent storage device, capture input/output telemetry for a workload on the storage system, determine one or more write reduction factors and one or more write invalidation factors for the workload based on the captured input/output telemetry, and allocate storage for the workload between the first persistent storage device and the second persistent storage device based on the one or more write reduction factors and the one or more write invalidation factors. Other embodiments are disclosed and claimed.

公开(公告)号：US20190146698A1

公开(公告)日：2019-05-16

申请号：US16229679

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Marcin Pioch ,  Michael Mesnier ,  Anand Ramalingam ,  Benjamin Boyer ,  Kapil Karkra ,  Piotr Wysocki

IPC: G06F3/06 ,  G06F12/1009

Abstract: A system including a storage drive and a semiconductor apparatus coupled to the storage drive, is provided. The semiconductor apparatus may include one or more substrates and logic coupled to the one or more substrates, the logic coupled to the one or more substrates to: initiate managing resources of the storage drive and, if the storage drive loses capacity, determine an amount of capacity loss, create a reserved file that is associated with logical memory space in a file system, based on the amount of the capacity loss, and erase at least a portion of the reserved file so that logical memory space associated with an un-erased portion of the reserved file is usable by the storage drive.

公开(公告)号：US20190042114A1

公开(公告)日：2019-02-07

申请号：US16021722

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Michael Mesnier ,  Kapil Karkra ,  Piotr Wysocki ,  Jonathan Hughes ,  Brennan Watt ,  Sanjeev Trika ,  Anand Ramalingam

IPC: G06F3/06

Abstract: An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on host-provided information, and refresh the determined set of data on a persistent storage media as a background operation. Other embodiments are disclosed and claimed.

公开(公告)号：US12118240B2

公开(公告)日：2024-10-15

申请号：US16987748

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Benjamin Walker ,  Sanjeev Trika ,  Kapil Karkra ,  James R. Harris ,  Steven C. Miller ,  Bishwajit Dutta

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0689

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to maintain a respective lookup table for each of two or more persistent storage devices in a persistent memory outside of the two or more persistent storage devices with a first indirection granularity that is smaller than a second indirection granularity of each of the two or more persistent storage devices, buffer write requests to the two or more persistent storage devices in the persistent memory in accordance with the respective lookup tables, and perform a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of the buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity. Other embodiments are disclosed and claimed.

公开(公告)号：US11132215B2

公开(公告)日：2021-09-28

申请号：US16454703

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Maksymilian Kunt ,  Piotr Wysocki ,  Slawomir Ptak ,  Kapil Karkra

IPC: G06F3/06 ,  G06F9/455 ,  G06F13/42 ,  H04L29/08

Abstract: Techniques to facilitate an out-of-band (OOB) management in a virtualization environment include examples of assigning an endpoint identifier to a domain mapped to physical memory addresses of one or more storage devices coupled with a computing platform. The domain may enable software or a device driver executed by a virtual machine (VM) to access, manage or control at least a portion of the one or more storage devices. Examples also include receiving or forwarding messages through an OOB communication link coupled with the computing platform to a management entity to facilitate OOB management of the software or the device driver executed by the VM.