公开(公告)号：US20190042242A1

公开(公告)日：2019-02-07

申请号：US15940774

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Dipankar DAS ,  Naveen K. MELLEPUDI ,  Mrinmay DUTTA ,  Arun KUMAR ,  Dheevatsa MUDIGERE ,  Abhisek KUNDU

IPC: G06F9/30 ,  G06F7/544 ,  G06F9/38

Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.

公开(公告)号：US20240126544A1

公开(公告)日：2024-04-18

申请号：US18399578

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Dipankar DAS ,  Naveen K. MELLEMPUDI ,  Mrinmay DUTTA ,  Arun KUMAR ,  Dheevatsa MUDIGERE ,  Abhisek KUNDU

IPC: G06F9/30 ,  G06F7/483 ,  G06F7/544 ,  G06F9/38 ,  G06N3/063

CPC classification number: G06F9/30014 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/384 ,  G06F9/3887 ,  G06N3/063 ,  G06F9/30065 ,  G06F2207/382

Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.

公开(公告)号：US20220214877A1

公开(公告)日：2022-07-07

申请号：US17704690

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Dipankar DAS ,  Naveen K. MELLEMPUDI ,  Mrinmay DUTTA ,  Arun KUMAR ,  Dheevatsa MUDIGERE ,  Abhisek KUNDU

IPC: G06F9/30 ,  G06F7/544 ,  G06F9/38 ,  G06N3/063 ,  G06F7/483

Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.

公开(公告)号：US20200310756A1

公开(公告)日：2020-10-01

申请号：US16370966

申请日：2019-03-30

Applicant: Intel Corporation

Inventor： Simon RUBANOVICH ,  Amit GRADSTEIN ,  Zeev SPERBER ,  Mrinmay DUTTA

IPC: G06F7/499 ,  G06F7/483 ,  G06F9/38 ,  G06F17/16

Abstract: Disclosed embodiments relate to performing floating-point addition with selected rounding. In one example, a processor includes circuitry to decode and execute an instruction specifying locations of first and second floating-point (FP) sources, and an opcode indicating the processor is to: bring the FP sources into alignment by shifting a mantissa of the smaller source FP operand to the right by a difference between their exponents, generating rounding controls based on any bits that escape; simultaneously generate a sum of the FP sources and of the FP sources plus one, the sums having a fuzzy-Jbit format having an additional Jbit into which a carry-out, if any, select one of the sums based on the rounding controls, and generate a result comprising a mantissa-wide number of most-significant bits of the selected sum, starting with the most significant non-zero Jbit.

公开(公告)号：US20200257527A1

公开(公告)日：2020-08-13

申请号：US16735381

申请日：2020-01-06

Applicant: Intel Corporation

Inventor： Dipankar DAS ,  Naveen K. MELLEMPUDI ,  Mrinmay DUTTA ,  Arun KUMAR ,  Dheevatsa MUDIGERE ,  Abhisek KUNDU

IPC: G06F9/30 ,  G06F7/483 ,  G06N3/063 ,  G06F9/38 ,  G06F7/544

Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.