公开(公告)号：US20230351542A1

公开(公告)日：2023-11-02

申请号：US18306033

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Naveen K. MELLEMPUDI ,  DHEEVATSA MUDIGERE ,  DIPANKAR DAS ,  SRINIVAS SRIDHARAN

IPC: G06T1/20 ,  G06F5/01 ,  G06F7/501 ,  G06F7/523 ,  G06F7/544 ,  G06F17/15 ,  G06F17/16 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06T1/20 ,  G06F5/01 ,  G06F7/501 ,  G06F7/523 ,  G06F7/5443 ,  G06F17/153 ,  G06F17/16 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06F2207/382 ,  G06F2207/4824

Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to convert elements of a floating-point tensor to convert the floating-point tensor into a fixed-point tensor.

公开(公告)号：US20240412318A1

公开(公告)日：2024-12-12

申请号：US18751799

申请日：2024-06-24

Applicant: Intel Corporation

Inventor： Naveen K. MELLEMPUDI ,  DHEEVATSA MUDIGERE ,  DIPANKAR DAS ,  SRINIVAS SRIDHARAN

IPC: G06T1/20 ,  G06F5/01 ,  G06F7/501 ,  G06F7/523 ,  G06F7/544 ,  G06F17/15 ,  G06F17/16 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to convert elements of a floating-point tensor to convert the floating-point tensor into a fixed-point tensor.

公开(公告)号：US20240126544A1

公开(公告)日：2024-04-18

申请号：US18399578

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Dipankar DAS ,  Naveen K. MELLEMPUDI ,  Mrinmay DUTTA ,  Arun KUMAR ,  Dheevatsa MUDIGERE ,  Abhisek KUNDU

IPC: G06F9/30 ,  G06F7/483 ,  G06F7/544 ,  G06F9/38 ,  G06N3/063

CPC classification number: G06F9/30014 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/384 ,  G06F9/3887 ,  G06N3/063 ,  G06F9/30065 ,  G06F2207/382

Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.

公开(公告)号：US20220327656A1

公开(公告)日：2022-10-13

申请号：US17730364

申请日：2022-04-27

Applicant: Intel Corporation

Inventor： Naveen K. MELLEMPUDI ,  DHEEVATSA MUDIGERE ,  DIPANKAR DAS ,  SRINIVAS SRIDHARAN

IPC: G06T1/20 ,  G06F5/01 ,  G06F7/501 ,  G06F7/523 ,  G06F7/544 ,  G06F17/15 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to quantize elements of a floating-point tensor to convert the floating-point tensor into a dynamic fixed-point tensor.

公开(公告)号：US20220214877A1

公开(公告)日：2022-07-07

申请号：US17704690

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Dipankar DAS ,  Naveen K. MELLEMPUDI ,  Mrinmay DUTTA ,  Arun KUMAR ,  Dheevatsa MUDIGERE ,  Abhisek KUNDU

IPC: G06F9/30 ,  G06F7/544 ,  G06F9/38 ,  G06N3/063 ,  G06F7/483

Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.

公开(公告)号：US20200257527A1

公开(公告)日：2020-08-13

申请号：US16735381

申请日：2020-01-06

Applicant: Intel Corporation

Inventor： Dipankar DAS ,  Naveen K. MELLEMPUDI ,  Mrinmay DUTTA ,  Arun KUMAR ,  Dheevatsa MUDIGERE ,  Abhisek KUNDU

IPC: G06F9/30 ,  G06F7/483 ,  G06N3/063 ,  G06F9/38 ,  G06F7/544

Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.