公开(公告)号：US20210096860A1

公开(公告)日：2021-04-01

申请号：US16833596

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Raanan SADE ,  Igor YANOVER ,  Stanislav SHWARTSMAN ,  Muhammad TAHER ,  David ZYSMAN ,  Liron ZUR ,  Yiftach GILAD

IPC: G06F9/30 ,  G06F9/50 ,  G06F9/38 ,  G06F9/48

Abstract: An apparatus and method for pairing store operations. For example, one embodiment of a processor comprises: a grouping eligibility checker to evaluate a plurality of store instructions based on a set of grouping rules to determine whether two or more of the plurality of store instructions are eligible for grouping; and a dispatcher to simultaneously dispatch a first group of store instructions of the plurality of store instructions determined to be eligible for grouping by the grouping eligibility checker.

公开(公告)号：US20230305742A1

公开(公告)日：2023-09-28

申请号：US18327474

申请日：2023-06-01

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Michael CHYNOWETH ,  Rajshree CHABUKSWAR ,  Muhammad TAHER

IPC: G06F3/06 ,  G06F11/34

CPC classification number: G06F3/0656 ,  G06F3/0673 ,  G06F3/0604 ,  G06F3/0653 ,  G06F11/3466

Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

公开(公告)号：US20200249866A1

公开(公告)日：2020-08-06

申请号：US15929272

申请日：2020-04-21

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Michael CHYNOWETH ,  Rajshree CHABUKSWAR ,  Muhammad TAHER

IPC: G06F3/06 ,  G06F11/34

Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.