公开(公告)号：US20230315453A1

公开(公告)日：2023-10-05

申请号：US17712018

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Lihu RAPPOPORT ,  Nir TELL ,  Rami BUSOOL ,  Eyal HADAS ,  Michael CHYNOWETH ,  Joseph OLIVAS ,  Christopher M. CHRULSKI

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3867

Abstract: An instruction pipeline includes a circuit that can generate a hardware event to indicate conditional branches, including the direction of taken branches. The circuit can generate a forward conditional branch indicator for an opcode when a conditional branch is taken to a forward location from the opcode. The instruction pipeline includes a counter to increment in response to the forward conditional branch indicator, which will indicate a frequency of forward conditional branches for the opcode.

公开(公告)号：US20230082290A1

公开(公告)日：2023-03-16

申请号：US17862708

申请日：2022-07-12

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Raanan SADE ,  Liron ZUR ,  Igor YANOVER ,  Joseph NUZMAN

IPC: G06F9/30 ,  G06F11/30 ,  G06F9/54 ,  G06F11/34

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

公开(公告)号：US20230176870A1

公开(公告)日：2023-06-08

申请号：US18160600

申请日：2023-01-27

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Raanan SADE ,  Liron ZUR ,  Igor YANOVER ,  Joseph NUZMAN

IPC: G06F9/30 ,  G06F9/54 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/30145 ,  G06F9/544 ,  G06F11/348 ,  G06F9/546 ,  G06F11/3037 ,  G06F9/30098

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

公开(公告)号：US20210200547A1

公开(公告)日：2021-07-01

申请号：US16729374

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Raanan SADE ,  Liron ZUR ,  Igor YANOVER ,  Joseph NUZMAN

IPC: G06F9/30 ,  G06F9/54 ,  G06F11/30

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

公开(公告)号：US20240211262A1

公开(公告)日：2024-06-27

申请号：US18419059

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Raanan SADE ,  Liron ZUR ,  Igor YANOVER ,  Joseph NUZMAN

IPC: G06F9/30 ,  G06F9/54 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/30145 ,  G06F9/30098 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F11/348

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

公开(公告)号：US20230305742A1

公开(公告)日：2023-09-28

申请号：US18327474

申请日：2023-06-01

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Michael CHYNOWETH ,  Rajshree CHABUKSWAR ,  Muhammad TAHER

IPC: G06F3/06 ,  G06F11/34

CPC classification number: G06F3/0656 ,  G06F3/0673 ,  G06F3/0604 ,  G06F3/0653 ,  G06F11/3466

Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

公开(公告)号：US20200249866A1

公开(公告)日：2020-08-06

申请号：US15929272

申请日：2020-04-21

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Michael CHYNOWETH ,  Rajshree CHABUKSWAR ,  Muhammad TAHER

IPC: G06F3/06 ,  G06F11/34

Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.