公开(公告)号：US20220174005A1

公开(公告)日：2022-06-02

申请号：US17673727

申请日：2022-02-16

Applicant: Intel Corporation

Inventor： Namrata LIMAYE ,  Daniel DALY ,  Anjali Singhai JAIN ,  Debashis CHATTERJEE ,  Venkata Suresh Kumar PARUCHURI

IPC: H04L45/60 ,  H04L45/586 ,  H04L45/021 ,  H04L45/00 ,  H04L45/24

Abstract: Examples described herein relate to a packet processing device that includes a programmable packet processing pipeline that is configured using a virtual switch. In some examples, the programmable packet processing pipeline is to receive configurations from multiple control planes via the virtual switch to configure packet processing actions. In some examples, the virtual switch is to provide inter-virtual execution environment communications. In some examples, the programmable packet processing pipeline is configured using a programming language.

公开(公告)号：US20210211467A1

公开(公告)日：2021-07-08

申请号：US17189219

申请日：2021-03-01

Applicant: Intel Corporation

Inventor： Helia A. NAEIMI ,  Sivakumar MUNNANGI ,  Namrata LIMAYE ,  Arvind SRINIVASAN ,  Gargi SAHA ,  Hung NGUYEN ,  Daniel DALY

IPC: H04L29/06

Abstract: Examples described herein relate to a Transport Layer Security (TLS) offload engine to: based on detection of encrypted data unassociated with a previously detected data header: search for one or more data headers; identify at least two candidate data headers for validation; and based on receipt of an indication that the at least two candidate data headers are valid, perform decryption of received data in one or more packets. In some examples, the TLS offload engine is to: based on receipt of an indication that one or more of the at least two candidate data headers is not a valid header, search for two or more other candidate data headers.