公开(公告)号：US09471494B2

公开(公告)日：2016-10-18

申请号：US14137432

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Neil M. Schaper ,  Joseph Nuzman ,  Larisa Novakovsky ,  Yen-Cheng Liu ,  Gilbert Neiger ,  Raj K. Ramanujan

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032 ,  G06F2212/222

Abstract: An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.

Abstract translation: 描述了用于执行高速缓存行回写操作的装置和方法。 例如，方法的一个实施例包括：发起针对特定线性地址的高速缓存行回写操作; 确定由线性地址识别的脏高速缓存行是否存在于由多个高速缓存级别组成的高速缓存层级的任何高速缓存上; 如果脏缓存行存在于其中一个缓存中，则将脏缓存行写回内存; 以及响应地将所述脏高速缓存行维持或置于所述层次结构的至少第一高速缓存中的排他状态。