公开(公告)号：US20190258502A1

公开(公告)日：2019-08-22

申请号：US16269058

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Vivekananthan SANJEEPAN ,  Leena K. PUTHIYEDATH ,  Chandan APSANGI ,  Nikhil TALPALLIKAR ,  Abinash K. BARIK

IPC: G06F9/455 ,  G06F3/06 ,  G06F12/1009 ,  G06F9/4401

Abstract: Examples may include techniques for persistent memory virtualization. Persistent memory maintained at one or more memory devices coupled with a host computing device may be allocated and assigned to a virtual machine (VM) hosted by the host computing device. The allocated persistent memory based on a file based virtual memory to be used by the VM. An extended page table (EPT) may be generated to map physical memory pages of the one or more memory devices to virtual logical blocks of the file based virtual memory. Elements of the VM then enumerate a presence of the assigned allocated persistent memory, create a virtual disk abstraction for the file based virtual memory and use the EPT to directly access the assigned allocated persistent memory.

公开(公告)号：US20210232504A1

公开(公告)日：2021-07-29

申请号：US17227220

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： James A. BOYD ,  Christopher E. COX ,  Nikhil TALPALLIKAR

IPC: G06F12/0891 ,  G06F12/0882 ,  G06F12/1081 ,  G06F12/1009 ,  G06F1/3234 ,  G06F11/30 ,  G06F11/32

Abstract: A memory subsystem with memory managed with coherent access can manage page table entries to enable putting the memory in a low power state. The memory control can change a page table entry for the memory prior to triggering the memory to enter the low power state. The change to the page table entry will cause a page fault for a subsequent access to the memory. The page fault will trigger handling the access to the memory with a fault routine, avoiding synchronous delay to the memory that would occur with normal access.