公开(公告)号：US20210247919A1

公开(公告)日：2021-08-12

申请号：US17221728

申请日：2021-04-02

Applicant: Intel Corporation

Inventor： Dean-Dexter R. EUGENIO ,  Arvind KUMAR ,  John R. GOLES ,  Christopher E. COX

IPC: G06F3/06 ,  G06F11/22 ,  G06F13/16

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

公开(公告)号：US20200219825A1

公开(公告)日：2020-07-09

申请号：US16824544

申请日：2020-03-19

Applicant: Intel Corporation

Inventor： Jaejin LEE ,  Christopher E. COX ,  Jun LIAO ,  Xiang LI

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A memory device includes a grounded molding. The memory device includes a substrate having a first surface for a memory die, where the substrate has ground vias through substrate to connect to a ground reference. The substrate has a ball grid array (BGA) on the opposite surface, including perimeter balls to connect to ground connections. The grounded molding includes an electrically conductive epoxy mold to cover the memory die, where the electrical conductivity of the molding, with the molding grounded can provide radio frequency interference (RFI) shielding.

公开(公告)号：US20190213148A1

公开(公告)日：2019-07-11

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX ,  Kuljit S. BAINS ,  George VERGIS ,  James A. McCALL ,  Chong J. ZHAO ,  Suneeta SAH ,  Pete D. VOGT ,  John R. GOLES

IPC: G06F13/16 ,  G06F13/40 ,  G11C14/00 ,  G11C11/4096

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4096 ,  G11C14/0009 ,  Y02D10/14 ,  Y02D10/151

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US20170103019A1

公开(公告)日：2017-04-13

申请号：US15388752

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Saher Abu Rahme ,  Christopher E. COX ,  Joydeep Ray

IPC: G06F12/0804 ,  G06F3/06 ,  G06F12/0897

CPC classification number: G06F12/0804 ,  G06F1/3225 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0868 ,  G06F12/0897 ,  G06F2212/60

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

公开(公告)号：US20220189532A1

公开(公告)日：2022-06-16

申请号：US17686287

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US20210005245A1

公开(公告)日：2021-01-07

申请号：US16879583

申请日：2020-05-20

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Bill NALE

IPC: G11C11/406 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US20200057718A1

公开(公告)日：2020-02-20

申请号：US16557628

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Saher Abu RAHME ,  Christopher E. COX ,  Joydeep RAY

IPC: G06F12/0804 ,  G06F12/0897 ,  G06F3/06 ,  G06F1/3225 ,  G06F12/0868

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

公开(公告)号：US20190042382A1

公开(公告)日：2019-02-07

申请号：US15857535

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Navneet DOUR ,  Christopher E. COX

IPC: G06F11/273 ,  G06F11/27 ,  G06F9/448

Abstract: A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.

公开(公告)号：US20180336943A1

公开(公告)日：2018-11-22

申请号：US15983009

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Kuljit S. BAINS ,  John B. HALBERT

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/409 ,  G11C16/24 ,  G11C16/10 ,  G11C7/00 ,  G11C7/08 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

公开(公告)号：US20170194962A1

公开(公告)日：2017-07-06

申请号：US15462664

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Nadav BONEN ,  Christopher E. COX ,  Alexey KOSTINSKY

IPC: H03K19/00 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.